JPS5558776A - Boosting circuit - Google Patents

Abstract

PURPOSE: To raise the efficiency of boosting, by adding switching transistors and turning them off at the timing of flowing of a through current to prevent the ineffective through current.

CONSTITUTION: PN channel pairs of transistors TP₅ and TN₅, TP₆ and TN₆, TP₇ and TN₇ constitute a CMOS inverter. Output signals H, I, J are used as gate signals for switching transistors G₅, G₆, G₇. When clock signals ϕ₁, ϕ₂ are both equal to -VSS₁, the switching transistors G₅, G₇ are turned on and a capacitor C₃ is charged to -VSS₁. At that time, another capacitor C₄ is not discharged because the switching transistor G₆ is off. When the clock signals ϕ₁, ϕ₂ are equal to VDD, the outputs H, J are inverted with delay of time constants τD₅, τD₇ and the transistors G₅, G₇ are turned on and the other G₆ is turned on and the capacitor C₄ is charged to -2VSS₁. When the clock signals ϕ₁, ϕ₂ become -VSS₁, the transistor G₇ is kept off because the delay of the output I due to a time constant τD₆ is large. This results in interrupting a through current from flowing. If a plurality of such boosting circuits are provided, a capacitor can be charged to -3VSS₁.

COPYRIGHT: (C)1980,JPO&Japio