JPH0116070Y2 - - Google Patents

Description

[Detailed explanation of the invention] This invention is a invention that allows the power-on clear circuit to operate reliably without malfunction.

More specifically, the idea is to ensure that the power-on clear circuit operates when the power is turned on, and then prevents the power-on clear circuit from operating due to disturbances such as noise.

Conventionally, a power-on clear circuit as shown in Figure 1 has been used in C-MOS circuits for watches. 1 is a low resistance using a MOS transistor, 2 is a capacitor, and 3 is a C-MOS inverter.
Now, when the power is turned on, a current of charge flows through resistor 1 to capacitor 2, as shown in Figure 2 a. Due to this charging current, the voltage across capacitor 2 becomes as shown in Figure 2b. If the threshold voltage of inverter 3 in Figure 1 is _VTH in Figure 2b, the output of the inverter circuit will be as shown in Figure 2c.

The power-on clear circuit utilizes the fact that the inverter output becomes "1" when the power is turned on in this way, and uses this pulse to clear other C-
Initialize other logic circuits in the MOS-IC,
By turning the logic circuit into an "undefined" state when the power is turned on, this prevents the display element from displaying a random or non-existent display.

This power-on clear circuit operates only when the power is turned on, and it would be a problem if it were to operate after the power is turned on. This is because if the power-on clear circuit is activated for some reason while the time is being counted and displayed and the logic circuit is "initialized", the time will be incorrect.

Conventional power-on clear circuits sometimes have problems such as noise or activation due to the power supply voltage generated when driving speakers, lamps, etc. The present invention is an improvement on this point, but before explaining the present invention, the mechanism by which the power-on clear circuit operates due to fluctuations in the power supply voltage will be explained below based on Figure 3 a and b.

FIG. 3a shows a conventional power-on clear circuit, and FIG. 3b shows its operation diagram.

Assuming that the power supply voltage is now stable between V _DD and V _SS , a voltage V _C equal to this voltage is charged across the capacitor 32. Suppose that at time T _O , the power supply voltage suddenly increases from V _DD to V _SS '. Since the capacitor 32 is connected to the V _SS side, a voltage equal to V _C from V _SS ' appears momentarily on the capacitor 32, which is then charged via the resistor 31 to V _DD to V _SS '. It will be done. During this process, if V _C is smaller than the inverter's threshold voltage V _TH ', a "1" is output at the output of the inverter circuit 33, and this signal continues until the voltage across the capacitor reaches V _TH '. Therefore, a power-on clear pulse is generated at this time, and other logic circuits are initialized.

The threshold voltage of the inverter 33 changes from V _TH to V _TH ' as the power supply voltage changes.
Since this is widely known in C-MOS circuits, this explanation will be omitted. Generally, the threshold voltage of an inverter circuit is 1/2 of the power supply voltage.
It becomes.

Next, the present invention will be explained in detail, showing an example of its implementation in Fig. 4.

Note that FIG. 5 is an operational diagram of FIG. 4.

In FIG. 4, the conductivity coefficients of each of the P channel transistor 43 and the N channel transistor 44 constituting the C-MOS inverter circuit are
Let K _P and K _N be such that K _P ≪K _N.

In this way, the threshold voltage of the inverter is approximately equal to the threshold voltage of transistor 44 (V _TN ).

Let's consider the case where a fluctuation in the power supply voltage occurs in a circuit set up in this way. I will explain based on Figure 5. Similar to Figure 3 a and b, when the power supply voltage is between V _DD and V _SS , the capacitor 42
A voltage (V _C ) equal to this power supply voltage is charged across both ends. When the power supply voltage increases from V _DD to V _SS ', the inverter's threshold voltage remains approximately V _TN regardless of fluctuations in the power supply voltage.

Therefore, V _C = |V _DD −V _SS | and since V _C > V _TN , V _C will always be higher than the inverter's threshold voltage at the time _TO when the power supply voltage fluctuates. Therefore, it is absolutely impossible for the inverter's output to become "1" due to fluctuations in the power supply voltage.

The above can be said to be a successful application of the characteristics of the threshold voltage of a C-MOS inverter. In other words, the threshold voltage of a C-MOS inverter is V _TH = α (V _DD - V _TP ) + V _TN /1 + α, where α = √ _{P N.}

In the formula, V _TP ...Threshold voltage of P-channel transistor VT _N ...Threshold voltage of N-channel transistor K _P ...Conductivity coefficient of P-channel transistor K _N ...Conductivity coefficient of N-channel transistor.

In a general C-MOS circuit, V _TH = V _DD /2 is obtained by setting V _TP = V _TN α = 1.

The inverter threshold voltage is 1/2 of the power supply voltage, which has advantages such as a wider operating power supply voltage range and a wider noise margin. This invention is an inverter used in a power-on clear circuit, and by setting V _TH = V _TN with α≪1, the threshold voltage of the inverter is prevented from being affected by the power supply voltage. This provides a circuit in which the voltage across the capacitor never becomes lower than the inverter's threshold voltage, no matter what power supply voltage is applied.

Next, I will explain why the conductivity coefficient ratio of the transistors that make up the inverter is set to 10 or more.

As explained earlier, generally K _P = K _N.

If this is not necessary, design the transistors with the same gate dimensions. This makes mask design easier, so use this when the circuit characteristics are not a big issue.

In this case, since the carrier holes and electrons have different mobilities, and 2×K _P = K _N , and the ratio of conductivity coefficients when an inverter is configured is 1:2.

As mentioned above, the reason why the ratio is 1:10 or 10:1 or more is because it seems that the product was designed with the expectation of the same effect as the present invention.

Also, if the ratio is 10 or more, the formula is Therefore, the value is much closer to the V _SS side than the normal value, and the purpose of this invention can be achieved.

In addition, in the case shown in Figure 6 where the capacitor V _DD is connected to the side, if K _P > K _N , a power-on clear circuit that is resistant to fluctuations in the power supply voltage is required for the same reason as in the case of Figure 4. You can make it.

As explained above, the present invention provides a power-on clear circuit that operates extremely stably against fluctuations in battery voltage that occur during relatively large current loads such as when driving a motor, lamp, or speaker in an electronic watch. We can provide it. In addition, conventionally a shield plate was inserted to prevent the operation of the power-on clear circuit due to static electricity noise, but this is no longer necessary, and has a great effect on providing a stable circuit that does not malfunction and reducing costs. there is.

[Brief explanation of the drawing]

Figure 1 is a conventional power-on clear circuit diagram. Second
Figures a to c are explanatory diagrams of the operation in Figure 1, and Figure 2 a.
is a waveform diagram of the current flowing through resistor 1, Figure 2b is a waveform diagram of the input voltage of inverter 3, and Figure 2c is a waveform diagram of the output voltage of inverter 3. FIG. 3a is a conventional power-on clear circuit diagram, and FIG. 3b is an explanatory diagram of its operation. FIG. 4 is a diagram showing an embodiment of the present invention, and FIG. 5 is an explanatory diagram of the operation of the circuit of FIG. 4 when the power supply voltage fluctuates. Figure 6 is a diagram showing another embodiment of the present invention. 41,62...Resistor, 42,61...Capacitor, 43,63...P channel transistor, 4
4,64...N channel transistor.

Claims (1)

[Scope of utility model registration request] A resistive element and a capacitive element are connected in series between power supplies, and a connection point between the resistive element and the capacitive element includes a first transistor on the resistive element side and a second transistor on the capacitive element side. A power-on clear circuit for an electronic watch, characterized in that, in a circuit connected to an input side of a MOS inverter, the first transistor has a conductivity coefficient of 1, and the second transistor has a conductivity coefficient of 10 or more.