JPH0352010A - Power source switching circuit - Google Patents

Power source switching circuit

Info

Publication number
JPH0352010A
JPH0352010A JP18806789A JP18806789A JPH0352010A JP H0352010 A JPH0352010 A JP H0352010A JP 18806789 A JP18806789 A JP 18806789A JP 18806789 A JP18806789 A JP 18806789A JP H0352010 A JPH0352010 A JP H0352010A
Authority
JP
Japan
Prior art keywords
power supply
mos transistor
substrate
supply terminal
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18806789A
Other languages
Japanese (ja)
Inventor
Yuji Hishiki
飛鋪 雄爾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP18806789A priority Critical patent/JPH0352010A/en
Publication of JPH0352010A publication Critical patent/JPH0352010A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To switch two power sources irrelevantly to whether their output voltages are large or small by switching the biases of the substrates of analog switches by using the other power sources and adding transistors(TR) to be driven by level shifting circuits in series with an analog switch. CONSTITUTION:The transistors 5 and 6 are added in series between two power source terminals and the TRs of the switch so as to securely turn off the TRs 1 - 4 of the switch even if the large-small relation between the output voltages of the two power sources -V1 and -V2 changes, and the TRs are driven by the level shifting circuits 7 and 9. Further, MOS TRs 5 and 6 are provided between the 1st and 2nd power source terminals and substrate so as to switch the potentials of the substrate of the MOS TRs 1 - 4 constituting the switch, and their gates are connected to the 2nd and 1st power source terminals in a cross state. Consequently, the two power sources can be switched without reference to whether their output voltages are large or small.

Description

【発明の詳細な説明】[Detailed description of the invention]

〔産業上の利用分野J 本発明は,半導体集積回路(以下ICと称する)に搭載
され、2つの異なる電源を切換えてIC内部の回路に電
源を供給する電源切換回路に関する.
[Industrial Application Field J] The present invention relates to a power supply switching circuit installed in a semiconductor integrated circuit (hereinafter referred to as an IC), which switches between two different power supplies to supply power to circuits inside the IC.

【発明の概要1 本発明は、アナログスイッチの基板のバイアスを互いに
他の電源を用いて切換えること,及びレベルシフト回路
により駆動されるトランジスタを上記アナログスイッチ
に直列に付加することにより,異なる2つの電源のうち
の一方を制御信号により導通させている間に他方の電源
との電位の大小関係が変化しても貫通電流が流れないよ
うにしたものである. 〔従来の技術】 例えば,時計用のICでは、ブザーやランプを駆動する
際一時的に電源電圧が低下するのを防ぐため,第2図の
ような電源切換回路が従来から用いられている.この電
源切換回路は、ドレインを負の電源電圧−Vlに接続し
、ソース及び基板を負の電源電圧−VSSに接続し,制
御入力信号端子10より入力される制御信号を反転する
インバータ8にゲートが接続されたNチャネルMOSト
ランジスタ2と,ドレインを電源一VSSに接続しソー
ス及び基板を電源−v2に接続しゲートを制御人力端子
10に接続したNチャネルMOSトランジスタ3とから
成り,制御信号により負の電源電圧−vSSとして負の
電源電圧−Vtと負の電源電圧−V2のいずれか一方の
電源電圧を出力する形をとっている.時計用のICでは
、通常1.5Vと3vの2つの電源系があり、ICの基
板をGNDとして負の電源−Vlに−1.5V、負の電
源一V2に−3vをそれぞれ接続して制御信号を印加す
ることにより、ブザーやランプの駆動時に一時的にIC
内部の電源をl 5Vから−3vに切換えている.
[Summary of the Invention 1] The present invention enables two different analog switch substrate biases to be switched using different power supplies, and a transistor driven by a level shift circuit to be added in series to the analog switch. This prevents through-current from flowing even if the magnitude relationship between the power supplies and the other power supply changes while one of the power supplies is turned on by a control signal. [Prior Art] For example, in ICs for watches, a power supply switching circuit as shown in Fig. 2 has traditionally been used to prevent a temporary drop in power supply voltage when driving a buzzer or lamp. This power supply switching circuit has a drain connected to a negative power supply voltage -Vl, a source and a substrate connected to a negative power supply voltage -VSS, and a gate connected to an inverter 8 that inverts a control signal inputted from a control input signal terminal 10. It consists of an N-channel MOS transistor 2, which is connected to a power source, and an N-channel MOS transistor 3, whose drain is connected to a power supply voltage VSS, whose source and substrate are connected to a power source voltage V2, and whose gate is connected to a control terminal 10. The configuration is such that either one of the negative power supply voltage -Vt and the negative power supply voltage -V2 is output as the negative power supply voltage -vSS. A watch IC usually has two power supply systems, 1.5V and 3V, and with the IC board connected to GND, -1.5V is connected to the negative power supply -Vl, and -3V is connected to the negative power supply -V2. By applying a control signal, the IC can be temporarily turned off when driving a buzzer or lamp.
The internal power supply is switched from l5V to -3V.

【発明が解決しようとする課題】[Problem to be solved by the invention]

第2図に基いて説明した従来の回路においては,負の電
源電圧−v2が負の電源電圧−Vlよりも高い電位にな
ると,トランジスタの基板とドレイン間のダイオードが
順方向にバイアスされ,電流が流れる.このため.トラ
ンジスタがスイッチインク素子として正常に機能しない
ことになる.従って,この回路では切換られる電源電圧
の大小関係が一定である必要があり、一般の電源切換ス
イッチとしては使えないという欠点があった. 本発明の目的は、従って、従来技術における上述の問題
点を解決することができる改善された電源切換回路を提
供することにある. 〔課題を解決するための千段】 上記目的を達成するために、本発明では、2つの電源の
出力電圧の大小関係が変わってもスイッチのトランジス
タが確実にOFFできるように,2つの電源端子とスイ
ッチのトランジスタとの間に直列にトランジスタを追加
し、レベルシフト回路により駆動する構成とした.さら
に、スイッチとなるMOSトランジスタの基板の電位を
切換えるために、第1及び第2の電源端子と上記基板と
の間にそれぞれMOSトランジスタを設け,各々のゲー
トを第2及び第1の電源端子にたすき状に接続した.
In the conventional circuit explained based on FIG. 2, when the negative power supply voltage -v2 becomes higher than the negative power supply voltage -Vl, the diode between the substrate and drain of the transistor is forward biased, and the current flows. For this reason. The transistor will not function properly as a switching element. Therefore, in this circuit, the magnitude relationship of the power supply voltage to be switched must be constant, and it had the disadvantage that it could not be used as a general power supply changeover switch. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an improved power switching circuit capable of overcoming the above-mentioned problems in the prior art. [A Thousand Steps to Solve the Problem] In order to achieve the above object, in the present invention, two power supply terminals are connected so that the transistor of the switch can be turned off reliably even if the magnitude relationship between the output voltages of the two power supplies changes. A transistor was added in series between the switch and the switch transistor, and the structure was configured to be driven by a level shift circuit. Further, in order to switch the potential of the substrate of the MOS transistor serving as a switch, MOS transistors are provided between the first and second power supply terminals and the above substrate, and each gate is connected to the second and first power supply terminal. Connected like a sash.

【作用} 制御入力端子がGNDレベルに接続されている時、負の
電圧−VSSは負の電圧−V2と等しくなっている.I
C内部はこの負の電圧一V2により駆動されるため,制
111{”号の振幅4JGNDレベルから負の電圧−V
2の間になる.負の電圧−V2が負の電圧一Vlよりも
高い電位(電圧としては低い)になると,制御信号の振
幅が負の電圧一Vlよりも小さくなるので,レベルシフ
ト回銘により振幅を基準電圧GNDと負の電圧一Vlの
間に変換して,負の電源−vl側の直列トランジスタを
OFFする. また、たすき状に接続したトランジスタにより,基板の
電位は、負の電圧一Vtと負の電圧一v2のうち低い方
の電位にダイオードの順方向電圧分を加えた電位以上に
は上がらない.また、前記基板の電位は,負の電圧−V
lと負の電圧−V2のうちの低い方の値と,高い方から
MOSトランジスタのM{aを引いた値のうちの低い方
の値以下には下がらない. 【実施例】 以下、図面により本発明を詳細に説明する.第1図には
,NチャネルMOSトランジスタを用いた本発明の一実
施例が示されている.第1図において.MOSトランジ
スタ3とMOSトランジスタ4は制御信号によって駆動
され,負の電圧−VSSと負の電圧一V2の間をO N
/O F F Lている.MOSl−ランジスクlとM
OSトランジスタ2は,それぞれ前記制御信号と逆相の
信号で駆動され,負の電圧−VSSと負の電圧一Vlの
間をO N/O F Fさせる.MOSトランジスタl
のゲートには電源一Vtに接続された反転型レベルシフ
ト回路7の出力信号が入力され.MOSトランジスタ2
のゲートには電源−VSSに接続されたインバータ8の
出力信号が入力される.MOSトランジスタ4のゲート
には、負の電圧−V2に接続された正転型レベルシフト
回路の出力が接続されている.また、正転型レベルシフ
ト回路と、反転型レベルシフト回路と、インバータと、
MOSトランジスタ3には、制御信号入力端子10が接
続されている. 一方,前記MOSトランジスタ1.2、3、4の基板は
共通となっており、MOSトランジスタ5と6を介して
それぞれ電源−Vlと電源一V2に接続されている.M
OSl−ランジスタ5と6とは、それぞれ電源−v2と
電源一Vlとにより駆動されている. このような構成の電源切換回路において、制御入力端子
10がGNDレベルとなっている場合には、負の電圧−
vSSは負の電圧−v2に等しいレベルとなる.負の電
圧−Vlよりも負の電圧一v2が低い電位の時、基板の
電位は−V2よりもダイオードの順方向電圧以上高くは
ならない.何故なら、高くなろうとすると基板から電源
一V2に向かって電荷が流れるからである.また、基板
の電位が下がって−VlよりもMOSI−ランジスタの
閾値以上低い電位になると、トランジスタ6が導通し基
板と電源−v2の間に電荷が流れる。 この時、基板の電位が−V2よりも高ければ正帰還がか
かりトランジスタ6は一層深<ONする。 そのために、基板はー■2に固定される.また、この時
、基板の電位が−v2よりも低ければ,基板の電位はー
v2方向に引き上げられ、MOSトランジスタ6はOF
Fする.いずれにしてち、基板の電位は一定範囲を維持
する.MOSトランジスタ5と6とは2つの電源一v1
とーv2に対して対称であるから、この特性は負の電圧
−vlと負の電圧一V2の大小関係に依らずに維持され
ることは明らかである, 次に、負の電圧一Vlよりも負の電圧−V2の電位が高
くなった場合を考える.基板に関しては、上述した通り
でやはり一定電位内に維持される.ところで.IC内部
には電源として−vSSが供給されているから,制御信
号及びインバータ出力の振幅は基準電圧GNDと負の電
圧一v2の間である.一方、反転型レベルシフト回路7
の出力の振幅は基準電圧GNDと負の電圧一Vlの間で
あるから、負の電圧−Vlが負の電圧−v2よりも十分
低くなったと仮定しても、MOSトランジスタlは確実
にOFFする. 制御信号人力端子の電位がーvSSの場合にも、本発明
の回路の対称性から同様の説明により回路動作が示され
るため、ここでは省略する.なお、上記実施例では、N
チャネルMOSI−ランジスタを用いた場合の一実施例
について説明したが.本発明は上記実施例に限定される
ちのでは無く,PチャネルMOSトランジスタ、さらに
は他の電界効果型トランジスタを用いた回路にも適用す
ることができ、同様の効果を得ることができるものであ
る.
[Operation} When the control input terminal is connected to the GND level, the negative voltage -VSS is equal to the negative voltage -V2. I
Since the inside of C is driven by this negative voltage -V2, the negative voltage -V
It will be between 2. When the negative voltage -V2 becomes a higher potential (lower in terms of voltage) than the negative voltage -Vl, the amplitude of the control signal becomes smaller than the negative voltage -Vl, so the amplitude is changed to the reference voltage GND by level shift. and the negative voltage -Vl, and turn off the series transistor on the negative power supply -vl side. Furthermore, due to the transistors connected in a sash-like configuration, the potential of the substrate does not rise above the potential equal to the lower of the negative voltage 1Vt and the negative voltage 1V2 plus the forward voltage of the diode. Further, the potential of the substrate is a negative voltage −V
It does not fall below the lower of the lower value of l and the negative voltage -V2, and the value obtained by subtracting M{a of the MOS transistor from the higher value. [Example] The present invention will be explained in detail below with reference to the drawings. FIG. 1 shows an embodiment of the present invention using an N-channel MOS transistor. In Figure 1. MOS transistor 3 and MOS transistor 4 are driven by a control signal, and are turned ON between negative voltage -VSS and negative voltage -V2.
/OFF L is here. MOSl-Landisk l and M
The OS transistors 2 are each driven by a signal having a phase opposite to the control signal, and are turned ON/OFF between a negative voltage -VSS and a negative voltage -Vl. MOS transistor l
The output signal of the inverting level shift circuit 7 connected to the power supply Vt is input to the gate of the . MOS transistor 2
The output signal of the inverter 8 connected to the power supply -VSS is input to the gate of the inverter 8. The gate of the MOS transistor 4 is connected to the output of a non-inverting level shift circuit connected to a negative voltage -V2. Further, a normal rotation type level shift circuit, an inversion type level shift circuit, an inverter,
A control signal input terminal 10 is connected to the MOS transistor 3. On the other hand, the MOS transistors 1, 2, 3, and 4 have a common substrate, and are connected to the power source -Vl and the power source -V2 via MOS transistors 5 and 6, respectively. M
The OSl-transistors 5 and 6 are driven by the power supply -v2 and the power supply -Vl, respectively. In a power supply switching circuit having such a configuration, when the control input terminal 10 is at the GND level, a negative voltage -
vSS becomes a level equal to the negative voltage -v2. When the negative voltage -V2 is a lower potential than the negative voltage -Vl, the potential of the substrate does not become higher than -V2 by more than the forward voltage of the diode. This is because when the voltage increases, charge flows from the board toward the power supply V2. Further, when the potential of the substrate decreases to a potential lower than -Vl by more than the threshold value of the MOSI transistor, the transistor 6 becomes conductive and charge flows between the substrate and the power source -v2. At this time, if the potential of the substrate is higher than -V2, positive feedback is applied and the transistor 6 is turned on even further. For this purpose, the board is fixed at -■2. Moreover, at this time, if the potential of the substrate is lower than -v2, the potential of the substrate is pulled up in the -v2 direction, and the MOS transistor 6 is turned off.
F. In any case, the potential of the substrate remains within a certain range. MOS transistors 5 and 6 are connected to two power supplies -v1
Since it is symmetrical with respect to -v2, it is clear that this characteristic is maintained regardless of the magnitude relationship between negative voltage -vl and negative voltage -V2.Next, from negative voltage -Vl, Consider the case where the potential of negative voltage -V2 becomes high. As for the substrate, it is maintained within a constant potential as described above. by the way. Since -vSS is supplied as a power source inside the IC, the amplitude of the control signal and the inverter output is between the reference voltage GND and the negative voltage -v2. On the other hand, the inverting level shift circuit 7
The amplitude of the output of is between the reference voltage GND and the negative voltage -Vl, so even if it is assumed that the negative voltage -Vl becomes sufficiently lower than the negative voltage -v2, the MOS transistor l will definitely turn off. .. Even when the potential of the control signal input terminal is -vSS, the circuit operation will be shown by the same explanation due to the symmetry of the circuit of the present invention, so the explanation will be omitted here. Note that in the above embodiment, N
An embodiment using channel MOSI transistors has been described. The present invention is not limited to the above embodiments, but can be applied to circuits using P-channel MOS transistors and other field effect transistors, and similar effects can be obtained. ..

【発明の効果】【Effect of the invention】

本発明によれば,上述の如く電源電圧の異なる2つの電
源を,その出力電圧の大小に関りなく切換ることか可能
であるため,バッテリーによるパックアップをするシス
テム等に用いることにより、外部回路が不要になるなど
極めて効果が大きいらのである.
According to the present invention, as described above, it is possible to switch between two power supplies with different power supply voltages regardless of the magnitude of their output voltages, so by using it in a battery backup system, etc., it is possible to switch between two power supplies with different power supply voltages. This is extremely effective as it eliminates the need for circuitry.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の電源切換回路の一実施例を示す回路図
,第2図は従来の1!源切換回路を示す回路図である. 1〜6 ・ 7 ・ ・ 8 ・ ・ ・・トランジスタ ・・反転型レベルシフト回路 ・・インバータ 9 ・正転型レベルシフト回路 10 ・制御信号入力端子 以 上
Fig. 1 is a circuit diagram showing one embodiment of the power supply switching circuit of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the power supply switching circuit of the present invention. FIG. 3 is a circuit diagram showing a power source switching circuit. 1 to 6 ・ 7 ・ ・ 8 ・ ・ ・ Transistor ・ Inverting type level shift circuit ・ Inverter 9 ・ Non-inverting type level shift circuit 10 ・ Control signal input terminal or higher

Claims (1)

【特許請求の範囲】[Claims] 電気的に接続された共通の基板上に設けられると共に、
直列に接続された第1、第2、第3、第4のMOSトラ
ンジスタと、前記第1のMOSトランジスタのソースに
接続された第1の電源端子と、前記第4のMOSトラン
ジスタのソースに接続された第2の電源端子と、前記共
通の基板上に設けられドレインを前記第1の電源端子に
、ソースを前記基板にそれぞれ接続した第5のMOSト
ランジスタと、前記共通の基板上に設けられドレインを
前記第2の電源端子に、ソースを前記基板にそれぞれ接
続した第6のMOSトランジスタと、前記第1の電源端
子に接続されその出力を前記第1のMOSトランジスタ
のゲートに入力する反転型レベルシフト回路と、前記第
2と第3のMOSトランジスタの共通のドレインに接続
された第3の電源端子と、前記第3の電源端子に接続さ
れ出力を前記第2のMOSトランジスタのゲートに入力
するインバータと、前記第2の電源端子に接続され出力
を前記第4のMOSトランジスタのゲートに入力する正
転型レベルシフタと、前記第3のMOSトランジスタの
ゲート及び前記反転型レベルシフトと前記インバータと
、前記正転型レベルシフタのそれぞれの入力端子との共
通接続点である制御信号入力端子とから成る電源切換回
路。
Provided on a common electrically connected board,
first, second, third, and fourth MOS transistors connected in series; a first power supply terminal connected to the source of the first MOS transistor; and a first power terminal connected to the source of the fourth MOS transistor. a second power supply terminal provided on the common substrate; a fifth MOS transistor provided on the common substrate and having a drain connected to the first power supply terminal and a source connected to the substrate; a sixth MOS transistor having a drain connected to the second power supply terminal and a source connected to the substrate; and an inverted type MOS transistor connected to the first power supply terminal and inputting its output to the gate of the first MOS transistor. a level shift circuit, a third power supply terminal connected to a common drain of the second and third MOS transistors, and a third power supply terminal connected to the third power supply terminal and inputting an output to the gate of the second MOS transistor; an inverter connected to the second power supply terminal and inputting an output to the gate of the fourth MOS transistor; a gate of the third MOS transistor and the inverting level shifter; , and a control signal input terminal that is a common connection point with each input terminal of the normal rotation type level shifter.
JP18806789A 1989-07-20 1989-07-20 Power source switching circuit Pending JPH0352010A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18806789A JPH0352010A (en) 1989-07-20 1989-07-20 Power source switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18806789A JPH0352010A (en) 1989-07-20 1989-07-20 Power source switching circuit

Publications (1)

Publication Number Publication Date
JPH0352010A true JPH0352010A (en) 1991-03-06

Family

ID=16217128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18806789A Pending JPH0352010A (en) 1989-07-20 1989-07-20 Power source switching circuit

Country Status (1)

Country Link
JP (1) JPH0352010A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5892302A (en) * 1997-03-28 1999-04-06 Mitsubishi Electric Semiconductor Software Co. Ltd. Power switching circuit
JP2000196429A (en) * 1998-12-25 2000-07-14 Toshiba Corp Analog switch circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5892302A (en) * 1997-03-28 1999-04-06 Mitsubishi Electric Semiconductor Software Co. Ltd. Power switching circuit
JP2000196429A (en) * 1998-12-25 2000-07-14 Toshiba Corp Analog switch circuit

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