JP2940546B2 - Electronic clock with generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has an AC power generator capable of generating an AC electromotive force in a coil by electromagnetic induction, charging the generated power to a secondary power supply, and forming a clock circuit by the output of the secondary power supply. The present invention relates to a specific circuit configuration of an operating timepiece.

[0002]

2. Description of the Related Art Conventionally, in a wristwatch using a battery, it has been a major problem to extend the battery life. However, the size of batteries used in small wristwatches was naturally limited. As one means for solving these problems, as shown in US Pat. No. 4,653,931, a solar cell is provided on a display surface such as a dial, and a secondary battery or a charging capacitor is formed by the solar cell. It is an electronic wristwatch that charges and drives a clock circuit by the output of the secondary battery or capacitor. However, in this configuration, a black or blue solar cell is arranged on the dial, which gives a design limitation, and is not preferable as an electronic timepiece whose design is sold.

[0003] As another means, there has been a system in which an AC generator is provided in a timepiece and a clock circuit is driven by the generated power. In the case of this AC electromotive force, a rectifier circuit is required, and it is known that the secondary power supply is charged with the rectified power of the full-wave rectifier circuit using a die-to-bridge. However, in such a case, an overcharge prevention circuit for the secondary power supply is provided because the secondary power supply may be damaged if the secondary power supply is overcharged. -8
It is connected between a rectifier circuit and a secondary power supply (secondary battery) as disclosed in JP 0871. JP 52
FIG. 2 shows an overcharge prevention circuit 9 of Japanese Patent Publication No. 80871. The overcharge prevention circuit 9 constantly detects the voltage of the secondary battery 8, and the current from the secondary battery 8 always flows through the voltage detecting transistor in FIG. 2, that is, constantly discharges. Therefore, it is difficult for the rechargeable battery 8 to reach full charge, and at the time of non-power generation, the voltage of the rechargeable battery 8 continues to decrease due to discharge from the rechargeable battery 8, so that the driving of the clock circuit is not performed. It has a problem that it stops early or its drive becomes unstable.

[0004]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems in an electronic timepiece of this type having a full-wave rectifier circuit and an overcharge prevention circuit for a secondary power supply.
Provided is a small and inexpensive electronic timepiece with a generator that improves charging efficiency to a secondary power supply.

[0005]

An electronic timepiece with a power generator according to the present invention comprises at least a rotor, a stator, a coil for generating induced AC power in accordance with the rotation of the rotor, and a mechanism for rotating the rotor. A generator for converting electric power into electric energy, a rectifier circuit for rectifying the AC electromotive force induced in the coil, a chargeable secondary power supply for storing the power rectified by the rectifier circuit, and preventing overcharge of the secondary power supply. In an electronic timepiece with a power generation device having an overcharge prevention circuit, the rectification circuit is configured by bridge-connecting four rectification elements and is connected between the generator and the secondary power supply. It is connected between the generator and the rectifier circuit, and is connected in parallel to a coil constituting the generator.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the present invention in more detail, it will be described below with reference to the drawings.

FIG. 1 is an overall circuit diagram of an electronic wristwatch with a power generator similar to the present invention. First, the overall circuit diagram will be described. Reference numeral 1 denotes a power generating coil, which generates an AC induced voltage generated by the generator at both ends of the coil. Reference numeral 2 denotes a rectifier diode for half-wave rectification of the AC induced voltage, and charges the rectified power to the high-capacity capacitor 3. 4 is a capacitor 3
Is turned on when the voltage VSC of the capacitor 3 (hereinafter, the voltage value of the capacitor 3 is defined as VSC) reaches a predetermined voltage VLim, and the power generated in the power generation coil 1 is reduced. There is to bypass. The limiter setting voltage VLim is set so as to be equal to or higher than the maximum value of the voltage required in the circuit system and within the range of the rated voltage of the capacitor 3. Reference numeral 5 denotes a backflow prevention diode, which prevents a decrease in power generation efficiency due to an increase in the electromagnetic brake due to a reverse current, as will be described later. Reference numeral 7 denotes a multi-stage booster circuit, which switches the connection state of the booster capacitors 8 and 9, the capacitor 3, and the auxiliary capacitor 10 to change the electric charge of the capacitor 3 to the auxiliary capacitor 10.
To boost the voltage. Further, the multi-stage booster circuit 7 can switch between four types of boosting ratios of 3, 2, 1.5, and 1 and the boosted voltage is charged in the auxiliary capacitor 10. The circuit operates by the voltage VSS of the auxiliary capacitor 10 (hereinafter, the voltage value of the auxiliary capacitor 10 is defined as VSS). By employing such a multi-stage booster circuit 7, the operating voltage value of the circuit system is optimized. 11 is a VSS detection circuit for detecting the voltage of the auxiliary capacitor one 10, the reference voltage, with Vup <Vdown the relationship, there are two values Vu p and V down, VSS is V
The detection result is output to the multi-stage booster circuit 7 so that the boosting ratio is reduced when the voltage exceeds down, and the boosting ratio is increased when VSS falls below Vup. 12 is a clock circuit, 32
It includes an oscillation circuit for driving the crystal resonator 13 having an original oscillation of 768 Hz, a frequency dividing circuit, and a motor drive circuit for driving the motor-use coil 14, and operates at the voltage VSS.
The motor coil 14 drives a stepping motor for rotating the hands. 15 short T
An immediate start circuit is constituted by r and 16 series resistors, and when VSC is lower than a predetermined voltage VON, an immediate start operation is performed. The details will be described later. It is the VSC detection circuit 6 that detects that VSC has become VLim, VON. The vertical relationship between Vup and Vdown is such that VON <Vup <Vdown <VLim. The outline of the circuit has been described above, but a detailed description of the operation of each unit and its effects will be described below.

First, the principle of the AC generator used in this embodiment will be described with reference to FIG.

Reference numeral 15 denotes a means for generating a rotational torque, which is composed of a rotary weight whose center of rotation and center of gravity are eccentric. The rotational movement of the rotating means 15 is accelerated by a speed increasing wheel train 16 to rotate a rotor 17 as a power generating mechanism. The rotor 17 includes a permanent magnet 17a, and a stator 18 is disposed so as to cover the rotor 17. Coil 1 is magnetic core 1
The magnetic core 19 a and the stator 18 are fixed by screws 20. As the rotor 17 rotates, an electromotive force expressed as e = N (dφ / dt) is generated in the coil 1 and a current expressed as i = e / (R ² + (WL) ² ) is generated.

N: number of turns of the coil φ: number of magnetic fluxes passing through the magnetic core 22a t: time R: resistance of the coil W: rotation speed of the rotor 17 L: inductance of the coil This electromotive force is an alternating current having a substantially sin curve. Further, the rotor 17 and the hole of the stator 18 that encloses the rotor 17 are concentric, and enclose the rotor magnet over substantially the entire circumference. As a result, the force (gravitational torque) that tends to stop at the place where the rotor is located can be minimized.

Here, in the present invention, a full-wave rectifier circuit is used in place of the rectifier diode 2 constituting the rectifier circuit in FIG. 1, and this full-wave rectifier circuit is connected between the generator coil 1 and the capacitor 3 of the generator. Connected. FIG. 3 is a circuit diagram showing the power generation coil 1, the rectifier circuit, the capacitor 3, and the overcharge prevention circuit. In FIG. 3, a rectifier circuit includes four diodes 2a, 2b, 2c, and 2d connected in a bridge, and a generator coil 1 and a capacitor 3 of a generator.
An overcharge prevention circuit having a limiter Tr4 and a backflow prevention diode 5 is connected between the power generation coil 1 and the diode bridge, and is connected in parallel to the power generation coil 1. Here, when the charging of the capacitor 3 proceeds and becomes overcharged, the overcharge prevention circuit is turned on,
This is to prevent the capacitor 3 from being overcharged. In this case, since a full-wave rectifier circuit is connected between the capacitor 3 and the overcharge prevention circuit, no current flows from the capacitor 3 to the overcharge prevention circuit side. There is no discharge as in the publication No. 80871. Therefore, the driving of the clock circuit does not stop early, and the driving is stabilized. Further, in the present invention, since the rectifier circuit is a full-wave rectifier circuit, even if the generated power is AC, the AC full-wave passes through the rectifier circuit and is charged in the capacitor 3, so that in the case of half-wave rectification, In this way, there is no sudden rise in the induced voltage from the generator during the half-wave period on the non-rectified side, and there is no fear that the overcharge prevention circuit will be destroyed, or the withstand voltage of the overcharge prevention circuit will be reduced to a general circuit. It is sufficient to satisfy the normal level used, so the overcharge prevention circuit becomes large,
And it does not become expensive.

In the embodiment shown in FIG. 3, when the induced voltage generated in the power generating coil 1 has a high potential on the lower side of the coil 1 as shown in FIG. Here, if the backflow prevention diode 5 is not provided, even if the limiter Tr 4 is off, the current path of the dotted line 51 is taken through the parasitic diode 52 and only one side of the full-wave rectification is charged to the capacitor 3. Performance is reduced by half. Therefore, in the case of the embodiment shown in FIG. 3, the addition of the backflow prevention diode 5 is effective.

Next, a specific example of the multi-stage booster shown in FIG. 1 will be described with reference to FIG. The horizontal axis indicates time, and the vertical axis indicates the voltage VSC of the capacitor 3 (dotted line) and the voltage VSS of the auxiliary capacitor 10 (solid line). The above-mentioned VON, Vup, Vdown and VLim are respectively set as follows.

VON = 0.4V Vup = 1.2V Vdowm = 2.0V VLim = 2.3V Here, the section from t0 to t6 is a charging period mainly when the generator is operating, and after t6 It is assumed that no power is being generated, and this is the discharge period. In FIG. 4, the charging period and the discharging period are written on the same time scale, but in reality, the charging period is on the order of several minutes, and the discharging period is on the order of several days. From t0 to t1 and after t10, the operation is immediately started and will be described later. As VSC increases, VSC becomes a triple boosted state from t1 when VSC exceeds 0.4 V, and VSS is charged with a voltage of VSC × 3. When the battery is further charged, VSS reaches 2.0 V at t2. Thus, the boosting factor is reduced by one step, resulting in double boosting. Thereafter, when the charging is further advanced, VSS reaches 2.0 V at t3 and t4, respectively, and when VSS reaches 2.0 V, the boosting factor is reduced by one stage. That is, t1
t2 is triple boosting, t2 to t3 is double boosting, t3 to t4 is 1.5 times boosting, and t4 to t7 is 1 times boosting. In addition, 1
At the time of double boosting, VSC becomes equal to VSS, and the voltage increases. At this time, even if VSS reaches 2.0 V, the boosting ratio is not changed. The voltage further rises and VSC = VSS =
Between t5 and t6 when 2.3 V is reached, the limiter Tr4
Is turned on so that the voltage does not rise to 2.3 V or more. Next, in the discharge period after t6, 1.2 V is the switching point of the boosting ratio. In other words, when the voltage decreases, and when VSS = 1.2 V, the boosting ratio is increased by one step to 1.
It is assumed to be 5 times as high. Thereafter, each time VSS falls below 1.2 V, the boosting ratio increases by one step. Therefore, from t7
t8 is 1.5 times boost, t8 to t9 is 2 times boost, t9 to
t10 is boosted three times.

By employing such a step-up system, VSS, which is the drive power supply of the timepiece, can always maintain 1.2 V or more under the condition of VSC ≧ 0.4V, and the operating time of the timepiece can be extended. succeeded in. Note that Vup (1.2
V) is set to the minimum operation voltage of the stepping motor for the circuit and the pointer, and if there is no step-up and the system uses VSC as the driving voltage, VSC = 1.2 V or more, that is, the clock only during the period from t11 to t7. In the charging period, the time required for the clock to start moving is long, and in the discharging period, the time required for the clock to stop is short, resulting in a clock that is not desirable for the user.
Note that VON (0.4 V) is a voltage B at which startup is performed for triple boosting.
Therefore, the condition of VON × 3 ≧ Vup is set as follows.
It is obvious. V Lin (2.3 V) is set to 2.3 V with a margin since the withstand voltage of the capacitor 3 used in the present embodiment was 2.4 V.

Here, the switching of the boosting ratio is performed between VSS and Vup, Vup.
This is done by comparing down, which has the following effects. In the present invention, there are three detection voltages contributing to the switching of the boosting ratio. Immediate start ← → VON of the triple boosting and Vup and Vdowm described above.
In the case of a system that performs the detection by the voltage detection, four detection voltages are required. That is, immediately start ← → 3 times boost, 3
Double boost ← → double boost, double boost ← → 1.5 boost,
The detection voltage must be set at four switching points of 5 × boost →→ 1 × boost. Vss always boosts VSC is Vup
(1.2V) or more, it is necessary to provide a detection voltage as follows.

Immediate start ← → 3 times boost ・ ・ ・ 0.4V 3 times boost ← → 2 times boost ・ ・ ・ 0.6V 2 times boost ← → 1.5 times boost ・ ・ ・ 0.8V 1.5 times Step-up ← → one-time step-up... 1.2 V As described above, in the present embodiment, the detection voltage can be reduced by one, and the chip area of the IC can be reduced.
Further, even when the minimum operating voltage of the watch body is changed due to design or process reasons, the present embodiment also provides that VON
(0.4V) and Vup (0.2V) need only be changed. However, in a system in which boost switching is performed by VSC detection, it is necessary to change four detection voltages. That is,
To adjust the detection voltage by taking out the detection voltage adjustment terminal from the IC, many adjustment terminals are required.
According to this embodiment, the number of adjustment terminals can be reduced, and an increase in the IC chip area can be prevented. Further, in this embodiment, a four-valued multi-stage booster circuit is used. However, if the number of booster capacitors 8.9 is increased from three to three, an eight-value boost ratio can be set. That is, 1 times, ¹ _1/3-fold, 1.5
Times, 1 _^2/3-fold, 2-fold, 2.5-fold, 3-fold, an 8 value of 4 times boosting ratio switching system according VSC detection, it is necessary to provide a detection voltage to all of the above, the present In the embodiment, the detection voltage may be left as it is. As described above, according to the present embodiment, the system up of the boosting circuit can be easily performed.

Next, a specific configuration of the multi-stage booster circuit 7 is shown in FIG. TrI to Tr7 are FETs for reconnecting capacitors
The on / off of the FET is controlled by a boosting clock of 1 KHz. A dashed block 32 is a known up-down counter, and its 2-bit output S
A combination of A and SB holds a four-value boost ratio. FIG. 6 shows the relationship between SA and SB and the boost ratio. Mup input to the up / down counter 32 is
A signal output from the VSS output circuit 11 and VSS is Vup
The clock pulse is output when the voltage falls below (1.2 V), and "0" is active. Similarly, Mdown is equal to VSS
Is a black pulse output when the voltage exceeds Vdown (2.0 V). As described above, the boosting ratio is switched by the output of the VSS detection circuit 11. Hereinafter, the description of the logic signal will use the expressions "0" and "1", where "0" is the minus side (VSS side) of the auxiliary capacitor 10,
“1” indicates the + side (VDD side) of the auxiliary capacitor 10. Reference numeral 33 denotes a boost reference signal generating circuit which outputs CL1 and CL2 as boost reference signals based on the standard signals φ1K and φ2KM output in a divided cycle. Reference numeral 34 denotes a switching control circuit that outputs the above CL1 and CL2. Reference numeral 34 denotes a switching control circuit,
2 and a signal decoded from SA and SB is output.
The switching of one Tr7 is controlled. The above circuit operation is shown in the timing chart for each boost ratio.
FIG. 7 is a diagram showing a capacitor connection equivalent diagram for each boost ratio, and FIG. In FIG. 7, it means that Trn turns on when Trn becomes 1. FIG.
(A) is a switching control signal at the time of 1 × boosting, and T
r1,3,4,5,7 are always on. At this time, the capacitor value circuit becomes as shown in FIG. 8 (A), and all the capacitors 3, 8, 9, and 10 are connected in parallel, and the capacitor 3
Is equal to the voltage VSS of the auxiliary capacitor 10. FIG. 7 (B) shows a switching control signal at the time of 1.5 times boosting. In the section (A), Tr1, 3, and 6 are turned on.
In the section (b), Tr2, 4, 5, 7 are turned on. FIG. 8 (B) is a capacitor equivalent circuit at the time of 1.5 times boosting, and in the section of (A), the boosting capacitors 8 and 9 have 0.5 × VSC respectively.
Is charged, and 1.5 × VSC, which is the sum of VSC and 0.5 × VSC, is charged in the auxiliary capacitor 10 in the section (b). Similarly, (C) of FIG. 7 and FIG.
Tr1, 3, 5, 7 are turned on in the section (a), and Tr2, 4, 5, 7 are turned on in the section (b).
Is charged with 2 × VSC. Also, (D) is a triple boosting, and in the section (a), TrI, 3,5,7 are turned on, and in the section (b), Tr2,4,6 are turned on. Is charged 3 × VSC.

The signal "OFF" in FIG.
When the condition is ON (0.4 V), that is, in the immediate start state, the value is 1. At that time, the output of the boost reference signal generation signal 33 is stopped, and all of the transistors Tr1 to Tr7 are turned off, and the boost is not performed. . The outputs SA and SB of the up / down counter 32 are both initially set to 1, so that when the start is immediately released, the operation starts from triple boosting.

FIG. 9 shows a specific example of the VSS detection circuit. SP
1.2 and SP2.0 are sampling signals. When "1", the circuit is activated, and when "0", the circuit state is fixed so that no current is consumed. The portion 35 within the broken line is a known constant voltage circuit, and its output voltage is represented as VREG. 36 is VSS
Reference numeral 37 denotes a detection resistor, and reference numeral 37 denotes a reference voltage generation resistor. Intermediate tap respectively, when VSS = 1.2V, when the VM = VREG chromatography (r1 / r1 + r2 tens r3) VSS = 2.0V, VM = VREG (r1 + r2 / r1 tens r2 + r3) become set as I have. Reference numeral 38 denotes a transmission gate which detects when 1.2 V of VSS is detected.
The detection voltage is switched between when 0V is detected. 3
Reference numeral 9 denotes a comparator, which compares the vertical relationship between VSS and the detected voltage. 40 is a master latch with R1.2
, The output of the comparator 39 is latched. Similarly, 41 is also a master latch with R2.0,
The output of the comparator 39 is latched. A known differentiation circuit 42 outputs a Mup or Mdown clock pulse when the contents of the master latches 40 and 41 change, and changes the contents of the up / down counter 32 in FIG. φ8, φ64 and φ128 are reference signals output from the frequency divider, and φ8 is for initializing the master latches 40 and 41 and the differentiation circuit 42 for the next sampling. FIG. 10 shows a timing chart, and the above operation will be described. The first half is VSS> 2.0V
The second half is a chart when VSS <1.2V. R2.0, SP2.0, R1.2 and SP1.2 are output once every two seconds from a sampling signal generation circuit described later. When VSS> 2.0V, Mdown is output to lower the boosting ratio by one stage, and when VSS <1.2V, Mup is output to output the boosting ratio by one stage.

Next, the immediate start circuit will be described. The purpose is to make it possible to smoothly and surely shift to the boosting operation at the transition point where VSC becomes 0.4 V or less from 0.4 V or less. At the transition point, boosting needs to start, but in order for boosting to start, the oscillation circuit must be oscillating and the circuit must be operating. But,
Since the voltage at the transition point is as low as 0.4 V and the voltage is not boosted until the transition point, the circuit cannot operate. Further, if the transition point is set to a circuit operable voltage, there is no point in introducing a booster system. In order to solve the above problems, the immediate start circuit makes it possible to raise the VSS voltage at the transition point by a method different from that of the booster circuit. The specific circuit configuration is shown in FIG. VSC <VON (0.4
V), the “off” signal is 1
And the short-circuit Tr15 is turned off. The initialization of the booster circuit in FIG. 5 is performed by the off signal, and all the transistors Tr1 to Tr7 are turned off. When the generator operates in this state, the charging current i flows through the capacitor 3, and at that time, the series resistor 16 has the resistance value x i =
A voltage drop of v occurs. That is, the voltage of v + VSC is applied across the auxiliary capacitor 10 only when i is flowing. Although Tr3 and Tr4 are off at the time of immediate start, the auxiliary capacitor 10 can be charged with the voltage of v + VSC by the parasitic diode 43. The auxiliary capacitor 10 also serves as a smoothing capacitor. Thereafter, if the auxiliary capacitor 10 is charged with v + VSC, the circuit operation becomes possible. Series resistance 16
May be set so that the resistance value × i = v becomes VON (0.2 V) or more. Also, the "off" signal is "1" even when the oscillation is stopped and the circuit is not operating.
Is set on the circuit so that there is no problem with starting the immediate start circuit. Further, when VSC exceeds VON and the boost operation starts, the short-circuit Tr15 is turned on, and the power generation coil 1, the rectifier diode 2, the capacitor 3
The charging efficiency is enhanced by preventing an extra impedance component from being provided in the charging path formed by the above. Also VSC
Rise above the transition point means that the generator also operates and the charging current is flowing, so it is possible to immediately start the operation, that is, raise the voltage of VSS at the transition point. . Therefore, according to the present embodiment, the circuit system operates at the transition point, and it is possible to smoothly and surely shift to the boosting operation. Also, the instant start circuit of the present invention ensures that the clock operates when the generator is operating, so that the capacitor voltage is 0.4 V
Even below, you can easily monitor the clock operation. In other words, it is very effective for checking the operation at the time of factory shipment and selling PR at stores.

FIG. 12 shows a sampling signal generation circuit for detecting four types of voltages in this embodiment.
The four types of voltage detection are defined as Vu in the VSS detection circuit 11.
VON, VLim in p, Vdown detection and VSC detection circuit 6
It refers to detection. φ256M, φ1 / 2, φ64, φ1
Reference numerals 28M, φ16, and φ32 are reference signals output from the frequency divider, respectively, and generate each sampling pulse by decoding them. R2.0, R1.2, R
LIM and R0.4 are latched signals of each comparator, and SP2.0, SPI.2, SPLIM and SP0.4 are signals for operating each detection circuit. FIG. 13 is a time chart showing the generation process. Here, when the sampling pulse order, particularly when VSS reaches Vdown (2.0 V), the detection sampling signal SP2.0 for lowering the boosting factor by one stage and VSC reach VON (0.4 V). Sometimes, the detection sampling signal S for starting the boosting operation
A great effect can be obtained by setting P0.4 in the order as in this embodiment. FIG. 14A shows the operation in the sampling pulse order of the present embodiment, and FIG. 14B shows the operation when the sampling pulse order is reversed. First, in FIG. 14B, it is assumed that VSC was lower than VON (0.4 V) and was in an immediate start state before SP0.4a was output. At the time of output of SP0.4a, it is assumed that VSC ≧ VON, the start is immediately canceled, and the state shifts to the triple boosting state. At this time, VSS drops from the voltage in the immediate start state to 1.2 V (0.4 V × 3), but drops with a certain time constant without instantaneous drop. At this time, if the VSS voltage is sufficiently high (VSS> 2.0 V) at the time of immediate start, the following problem occurs. That is, at P1, VSS starts to drop to 1.2V, and when SP2.0a is continuously output at P2, if it is still VSS> 2,0V, the triple boosting state is required at the time of immediate start release. Despite that, the pressure is doubled. Then, VSS is
The voltage drops to 0.4 V × 2 = 0.8 V, falls below the lower limit of the circuit operating voltage, and the circuit stops. Therefore, VSC
Until the battery is charged to 0.6 V, the normal boosting operation cannot be performed, and the time from when the watch is stopped to when it starts to move during charging is lengthened, which is inconvenient. The reason for setting VSC = 0.6 V in the above is that even if double boosting occurs at the time of immediate start release, VSS = 2V
× 0.6V = 1.2V, and the circuit operation can be ensured. Therefore, in the present embodiment in FIG. 14A, the above problem is solved as follows. According to this, the order of SP2.0 and SP0.4 is shown in Fig. 14 (B).
Conversely, since SP00.4 is output, the period until the next output of SP2.0 is long. According to the present embodiment, the period is 2−0.047 = 1.953 sec.
This is 0.047 sec in FIG. 14 (B). First, when SP2.0a is output, it is still in the immediate start state, regardless of the step-up ratio switching. Next, when SP0.4a is output, the start is immediately canceled and the state shifts to the triple boosting state. VSS at P1 begins to drop toward 1.2V. Here, the period from SP0.4a to SP2.0b is 1.95.
P2 is output from SP2.0b because it is long enough with 3sec
VSS at that point will be below 2.0V. That is, at the time of output of SP2.0b, no detection is performed, and the boosting ratio can be maintained at 3 times. Specifically, the period from SP0.4 to the next SP2.0 may be set as follows. That is, a period longer than T (sec) obtained from ｛(i × r + VON) −VON × N｝ e × P (−T / CR) + VON × N <Vdown may be set.
Here, each symbol has the following meaning.

I: the maximum current value obtained from the AC generator r: the sum of the series resistance 16 and the internal resistance of the capacitor 3 VON: 0.4 V N: step-up magnification (N = 3 in this embodiment) C = auxiliary capacitor 10 R: Equivalent resistance value of switching Tr in the multi-stage booster circuit 7 Vdown: 2.0 V In the above equation, VSS is charged up to i × r + VON at the time of immediate start release, and VON has a time constant CR based on the voltage.
× N (0.2V), which means that the VSS voltage T (sec) after the immediate start release is Vdown
(2.0 V).

As described above, according to the present embodiment, it is possible to reliably shift from the immediate start state to the boosting operation simply by adjusting the output timing of the sampling pulses SP2.0 and SP0.4. In terms of logic, only the decoding condition of the sampling signal generation circuit of FIG. 9 is adjusted, and there is no addition. As a result, the capacitor voltage VSC, which is the purpose of introducing the booster circuit, is 0.4
When the voltage is equal to or higher than V, it is possible to guarantee that the clock operation can be performed even when the generator is not operating.

[0025]

As described above, according to the present invention, in an electronic timepiece with a power generator including a generator, a full-wave rectifier circuit, a secondary power supply, and an overcharge prevention circuit, the overcharge prevention circuit comprises Machine and the full-wave rectifier circuit,
In addition, since it is configured so as to be connected in parallel to the coil constituting the generator, the discharge from the secondary power supply to the overcharge prevention circuit side is reliably prevented by the full-wave rectifier, and the watch is stabilized for a long time. And an overcharge prevention circuit does not require an unnecessary high withstand voltage, so that a safe, small and inexpensive overcharge prevention circuit can be realized.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of a power generation electronic wristwatch similar to the present invention.

FIG. 2 is a principle diagram of an AC generator.

FIG. 3 is a diagram showing a limiter diagram of the present invention in a full-wave rectifier circuit.

FIG. 4 is a conceptual diagram of a boosting operation.

FIG. 5 is a detailed circuit diagram of a multistage booster circuit.

FIG. 6 is a diagram illustrating a method of storing a circuit for boosting magnification.

FIG. 7 is a time chart of a multi-stage booster circuit.

FIG. 8 is an equivalent circuit diagram of a capacitor connection of the multi-stage booster circuit.

FIG. 9 is a detailed circuit diagram of an auxiliary capacitor voltage detection circuit.

FIG. 10 is a time chart of the circuit diagram in FIG. 14;

FIG. 11 is a detailed circuit diagram of an immediate start circuit.

FIG. 12 is a circuit diagram of a sampling signal generation circuit for voltage detection.

FIG. 13 is a time chart of a sampling signal generation circuit.

FIG. 14 is a conceptual diagram showing a transition of an auxiliary capacitor voltage at the time of immediate start release.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Generating coil 2, 2a, 2b, 2c, 2d ... Rectifier diode 3 ... High capacity capacitor 4 ... Limiter 5 ... Backflow prevention diode 6 ... VSC detection circuit 7 ... Multi-stage booster circuit 8, 9 ... booster capacitor 10 ... auxiliary capacitor 11 ... VSS detection circuit 12 ... clock circuit 13 ... crystal oscillator 14 ... motor coil 17 ... rotor 18 ... Stator

Claims (1)

(57) [Claims] 1. A generator for converting mechanical energy into electric energy, comprising at least a rotor, a stator, a coil for generating induced AC power according to the rotation of the rotor, a generator for rotating the rotor, and a generator induced in the coil. An electronic timepiece with a power generating device, comprising: a rectifier circuit for rectifying AC electromotive force, a chargeable secondary power supply for storing power rectified by the rectifier circuit, and an overcharge prevention circuit for preventing overcharge of the secondary power supply. A rectifier circuit configured by bridge-connecting four rectifier elements and connected between the generator and the secondary power supply;
The electronic timepiece with a power generator, wherein the overcharge prevention circuit is connected between the generator and the rectifier circuit, and is connected in parallel to a coil constituting the generator.