JP3294194B2 - Electronic clock with generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention has a generator,
The present invention relates to a specific circuit configuration of a timepiece that charges a generated power of the generator to a secondary power supply and operates a clock circuit using an output of the secondary power supply.

[0002]

[0003]

2. Description of the Related Art In a conventional wristwatch, there is a system in which an AC generator is provided in a timepiece and a clock circuit is driven by the generated power. In this case, in order to keep the clock circuit running even when the generator is not operating and to keep the clock circuit running, the generated power is charged to the secondary battery or capacitor, and the clock circuit is constantly driven by the output. Need to be. However, the operating voltage range of the clock circuit is limited, and if the voltage of the secondary power supply (hereinafter, referred to as a secondary battery or a capacitor) is not charged to the operating voltage range lower limit of the circuit, the clock will operate. Did not move. If the capacity of the secondary power supply is reduced to shorten the charging time of the secondary power supply, the above problem can be solved to some extent. However, in such a case, the voltage drop time when the generator is not operating is conversely increased. And the time during which the clock can be used is shortened.

[0004]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a safe electronic timepiece with a power generating device that can use the clock for a long time even when the generator is not operating and that can prevent overcharging of the secondary power supply. I will provide a.

[0005]

An electronic timepiece with a power generator according to the present invention detects a power generator, a first power storage unit charged with an electromotive force of the power generator, and a voltage of the first power storage unit. First
A voltage detection circuit, an overcharge prevention circuit that prevents overcharge of the first power storage unit based on a detection voltage of the first voltage detection circuit, and a booster circuit that boosts the voltage of the first power storage unit A second power storage unit charged by an output of the boosting circuit, a second voltage detection circuit for detecting a voltage of the second power storage unit and outputting a detection result to the boosting circuit, and a clock circuit driven by a second power storage unit, the
The booster circuit is configured to generate the boosted voltage by the second voltage detection circuit.
That the compressed voltage exceeds the first reference voltage
When it is detected, the boosting ratio decreases and the first reference voltage
Voltage is below the second reference voltage
It is configured so that the boost factor increases when it is issued,
The ON voltage of the overcharge prevention circuit is a constant of the first power storage unit.
The first reference is set within the rated voltage.
The voltage is set lower than the ON voltage of the overcharge prevention circuit .

Further, in the electronic timepiece with a power generating device according to the present invention, in addition to the above-described configuration, the power generator is an AC generator, and the power generator has a full-wave rectifier circuit for rectifying an electromotive force of the power generator. One power storage unit is charged.

Further, an electronic timepiece with a power generator according to the present invention is characterized in that, in addition to the above-described configuration, the overcharge prevention circuit is connected between the AC generator and the rectifier circuit.

[0008]

[0009]

[0010]

[0011]

[0012]

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the present invention in more detail, it will be described below with reference to the drawings.

FIG. 1 is an overall circuit diagram of an electronic wristwatch with a power generating device according to the present invention. Reference numeral 1 denotes a power generating coil, which generates an AC induced voltage generated by the generator at both ends of the coil. Reference numeral 2 denotes a rectifier diode for half-wave rectification of the AC induced voltage, and charges the rectified power to the high-capacity capacitor 3. Reference numeral 4 denotes a limiter Tr for preventing the capacitor 3 from being overcharged. The limiter Tr is turned on when the voltage VSC of the capacitor 3 (hereinafter, the voltage value of the capacitor 3 is defined as VSC) reaches a predetermined voltage VLim. This is to bypass generated power. The limiter setting voltage VLim is equal to or higher than the maximum value of the voltage required in the circuit system, and the capacitor 3
It is set to fall within the range of the rated voltage of. 5
A backflow prevention diode prevents a decrease in power generation efficiency due to an increase in the electromagnetic brake due to a reverse current, as will be described later. Reference numeral 7 denotes a multi-stage booster circuit, which realizes boosting by transferring the charge of the capacitor 3 to the auxiliary capacitor 10 by switching the connection state of the booster capacitors 8 and 9, the capacitor 3 and the auxiliary capacitor 10.
Further, the multi-stage booster circuit 7 can switch between four types of boosting ratios of 3, 2, 1.5, and 1 and the boosted voltage is charged in the auxiliary capacitor 10. The circuit operates by the voltage VSS of the auxiliary capacitor 10 (hereinafter, the voltage value of the auxiliary capacitor 10 is defined as VSS). By employing such a multi-stage booster circuit 7, the operating voltage value of the circuit system is optimized. Reference numeral 11 denotes a VSS detection circuit for detecting the voltage of the auxiliary capacitor 110. The reference voltage has two values, Vup and Vdown, which have a relationship of Vup <Vdown.
If the voltage exceeds down (first reference voltage) , the boosting ratio is reduced. If VSS falls below Vup (second reference voltage) , the boosting ratio is increased.
Output the detection result. 12 is a clock circuit, 3
It includes an oscillating circuit for driving the quartz oscillator 13 having an original vibration of 2768 Hz, a frequency dividing circuit, and a motor driving circuit for driving the motor-use coil 14, and operates at the voltage VSS. The motor coil 14 drives a stepping motor for rotating the hands. 15 and shorting Tr of, constitutes an immediate start circuit in the series resistance of 16, when VSC is lower than a predetermined voltage VON, the immediate Star
The operation will be described later in detail. VSC
Is detected as VLim or VON as described above.
This is the SC detection circuit 6. The vertical relationship between Vup and Vdown is such that VON <Vup <Vdown <VLim. The outline of the circuit has been described above, but a detailed description of the operation of each unit and its effects will be described below.

First, the principle of the AC generator used in this embodiment will be described with reference to FIG.

Numeral 15 denotes a means for generating a rotational torque, which is composed of a rotary weight whose center of rotation and center of gravity are eccentric. The rotational movement of the rotating means 15 is accelerated by a speed increasing wheel train 16 to rotate a rotor 17 as a power generating mechanism. The rotor 17 includes a permanent magnet 17a, and a stator 18 is disposed so as to cover the rotor 17. Coil 1 is magnetic core 1
The magnetic core 19 a and the stator 18 are fixed by screws 20. When the rotor 17 rotates, an electromotive force expressed as e = N (dφ / dt) is generated in the coil 1 and i = e / (R ² + (W
L) ² ).

N: number of turns of the coil φ: number of magnetic fluxes passing through the magnetic core 19a t: time R: resistance of the coil W: rotation speed of the rotor 17 L: inductance of the coil This electromotive force is an alternating current having a substantially sin curve. Further, the rotor 17 and the hole of the stator 18 that encloses the rotor 17 are concentric, and enclose the rotor magnet over substantially the entire circumference. As a result, the force (gravitational torque) that tends to stop at the place where the rotor is located can be minimized.

The AC voltage obtained by such an AC generator is rectified and the capacitor 3 is charged. In the embodiment of the present invention, a half-wave rectification system having a simpler diode structure is used. By combining the generator of FIG. 2 with the half-wave rectification method, power generation efficiency equivalent to that of the full-wave rectification method is obtained. The reasons are described below.

FIG. 3A shows a half-wave rectifier circuit, and FIG. 3B shows a conventional full-wave rectifier circuit. 1 is a power generation coil, 3 is a capacitor, and 2 and 2a to d are rectifier diodes. FIG.
The half-wave rectifier circuit of A has only one diode in the charging loop, whereas the full-wave rectifier circuit of FIG. 3B has two diodes in the charging loop. Therefore, the voltage drop by the diode is doubled in the full-wave rectification method. FIG. 4 shows a comparison of the current waveforms of the respective systems. 24 is a reference line, 25 is a generated current in the conventional rectifier circuit, 26 is a generated current in the embodiment of the present invention, 27 is a loss due to voltage drop in the conventional rectifier circuit, and 28 is the present invention. FIG. 9 is a loss due to a voltage drop in the rectifier circuit according to the embodiment. Conventionally, the amount of electric charge stored in the power storage means is the area covered by 25 and 27. According to the embodiment of the present invention,
It is the area covered by 6 and 28. In this area comparison, there is almost no difference, and the power storage performance is the same. The reason why there is no difference in the power storage performance even when the half-wave rectification is performed as compared with the conventional full-wave rectification will be described below. During the period during which the half-wave rectification is cut (indicated by 29 in FIG. 4), no current flows through the coil 1 and, therefore, the brake torque applied to the rotor 17 is small, so that the movement of the rotary weight becomes faster. That is, the energy in the period of 29 is stored as the kinetic energy of the rotating weight and released during power generation. Therefore, the peak value of 26 is larger than that of 25. In addition, the rectification loss is advantageously reduced to two diodes and one half. As a result, despite the use of half-wave rectification, the power generation and storage performance is not worse than that of full-wave rectification.

FIG. 5 shows the structure of the limiter circuit.
FIG. 5A shows a limiter circuit according to the present invention, and FIG. 5B shows a general limiter circuit conventionally used. Reference numeral 4 denotes a limiter Tr for bypassing a current when the limiter operates, and is composed of a Pch MOSFET. This is because the clock IC requires low power consumption , and therefore uses the C-MOS process.
That is, the limiter Tr is configured in the IC,
Although it is a MOSFET, it is more advantageous in terms of space efficiency and cost than providing an external element outside the IC. In the conventional method in which the limiter Tr4 is connected in parallel with the capacitor 3, when the limiter Tr4 is turned on, the electric charge of the capacitor 3 is discharged through a path indicated by a dotted line 30. The purpose of the limiter is to prevent the capacitor 3 from being overcharged. In the conventional example, since the extra charge of the capacitor 3 is released, this seems to be good, but the limiter Tr4 is turned on. If left undisturbed, the charge will be discharged more than necessary. In order to avoid this, it is necessary to constantly monitor the voltage value of the capacitor 3 and immediately turn off the limiter Tr4 when VSC becomes lower than VLim. However, when the voltage detection circuit is constantly operated, the current consumption is greatly increased by the reference voltage generation circuit and the comparator circuit. Further, as a disadvantage of the conventional example,
When the limiter Tr4 is turned on, a high voltage is directly applied to the capacitor 3, and a large current flows through the limiter Tr4. To prevent the destruction of Tr4, it is necessary to use an extremely large Tr size, which leads to an increase in the IC size, which is disadvantageous in cost. In order to solve the above problem, the limiter circuit according to the present invention has a configuration shown in FIG. According to this, even if the limiter Tr4 is turned on, because of the rectifier diode 2,
The charge of the capacitor 3 does not discharge. Therefore, even after VSC becomes VLim, the fluctuation of VSC is only the amount of charge consumed by the clock body, so that the curve becomes a gentle decreasing curve, and it is not necessary to always operate the VSC detection circuit 6.
That is, the VSC detection circuit 6 only needs to be intermittently driven in a sampling manner, and the increase in current consumption can be minimized. Also, no large current flows through Tr4, and there is no need to increase the Tr size more than necessary. here,
The dotted line 31 indicates the direction of the bypass current by the limiter. When VSC reaches VLim, the supply current due to power generation may be cut off thereafter. Reference numeral 52 denotes a parasitic diode formed between the substrate and the drain of the limiter Tr. If the backflow prevention diode 5 is not provided, a current flows in the direction opposite to the dotted line 31 during power generation even when the limiter Tr4 is off. Then, as described in the section of the rectifier circuit, the brake torque of the generator increases, and the power generation efficiency decreases. This is a diode for preventing this. The addition of this backflow prevention diode 5 reduces the power consumption due to the intermittent operation of the voltage detection circuit by merely changing the connection position of the limiter Tr4.
The effects of miniaturization and securing the power generation performance are achieved.

The configuration of the limiter circuit according to the present invention is also effective when a bipolar transistor is used as the switching element. FIG. 6 shows a limiter circuit using a bipolar Tr as a switching element and having no backflow prevention circuit. FIG. 6A shows the case where the PNP type is used for the bipolar Tr, and FIG. 6B shows the case where the NPN type is used for the bipolar Tr. First, FIG. 6A
In this case, even when the PNP type Tr 44 is off, a reverse current 46 (dotted line) flows through the diode 44b formed between the collector and the base and the switching control circuit 45. Here, the switching control circuit 45
Changes the base of the PNP type Tr 44 to the high potential side level (PNP type Tr 4
4 (the same potential as the emitter of No. 4). Therefore, there is some current path that allows the current indicated by the dotted line 46 to flow through the switching control circuit 45.
6A, a reverse current 46 flows in FIG. 6A. Similarly, in FIG. 6B, a current flows between the diode 47a formed between the base and the collector of the NPN Tr 47 and the switching control circuit 48. Reverse current 49 as a path
(Dotted line) flows. Therefore, according to FIG. 7, which is another embodiment of the present invention, the bipolar Tr 44 or 47 is used.
By configuring the backflow prevention diode 5 in series with
A limiter circuit can be configured without cutting backflow current and reducing power generation performance.

Further, the limiter circuit configuration of the present invention is impeachable for a full-wave rectifier circuit using a diode bridge, and an embodiment thereof is shown in FIG. When the induced voltage generated in the power generation coil 1 has a high potential on the lower side of the coil 1 as shown in FIG. 8, the current path indicated by a dotted line 50 is taken in a normal state. Here, if the backflow prevention diode 5 is not provided, even if the limiter Tr 4 is off, it passes through the parasitic diode 52,
The current path indicated by the dotted line 51 is taken, and only one side of the full-wave rectification is charged in the capacitor 3, so that the charging performance is reduced by half. Therefore, the addition of the backflow prevention diode 5 of the present invention is effective for a full-wave rectifier circuit.

Next, a specific example of multi-stage boosting will be described with reference to FIG. The horizontal axis indicates time, and the vertical axis indicates the voltage VSC (dotted line) of the capacitor 3 and the voltage VSS of the auxiliary capacitor 10.
(Solid line). In addition, VON,
Vup, Vdown and VLim are respectively set as follows.

VON = 0.4V Vup = 1.2V Vdowm = 2.0V VLim = 2.3V Here, the section from t0 to t6 is a charging period mainly when the generator is operating, and after t6 It is assumed that no power is being generated, and this is the discharge period. In FIG. 9, the charging period and the discharging period are written on the same time scale. However, in reality, the charging period is on the order of several minutes, and the discharging period is on the order of several days. From t0 to t1 and after t10, the operation is immediately started and will be described later. As VSC increases, VSC becomes a triple boosted state from t1 when VSC exceeds 0.4 V, and VSS is charged with a voltage of VSC × 3. When the battery is further charged, VSS reaches 2.0 V at t2. Thus, the boosting factor is reduced by one step, resulting in double boosting. Thereafter, when the charging is further advanced, VSS reaches 2.0 V at t3 and t4, respectively, and when VSS reaches 2.0 V, the boosting factor is reduced by one stage. That is, t1
t2 is triple boosting, t2 to t3 is double boosting, t3 to t4 is 1.5 times boosting, and t4 to t7 is 1 times boosting. In addition, 1
At the time of double boosting, VSC becomes equal to VSS, and the voltage increases. At this time, even if VSS reaches 2.0 V, the boosting ratio is not changed. The voltage further rises and VSC = VSS =
Between t5 and t6 when 2.3 V is reached, the limiter Tr4
Is turned on so that the voltage does not rise to 2.3 V or more. Next, in the discharge period after t6, 1.2 V is the switching point of the boosting ratio. In other words, when the voltage decreases, and when VSS = 1.2 V, the boosting ratio is increased by one step to 1.
It is assumed to be 5 times as high. Thereafter, each time VSS falls below 1.2 V, the boosting ratio increases by one step. Therefore, from t7
t8 is 1.5 times boost, t8 to t9 is 2 times boost, t9 to
t10 is boosted three times.

By employing such a step-up system, VSS, which is the drive power supply of the timepiece, can always maintain 1.2 V or more under the condition of VSC ≧ 0.4V, and the operating time of the timepiece can be extended. succeeded in. Note that Vup (1.2
V) is set to the minimum operation voltage of the stepping motor for the circuit and the pointer, and if there is no step-up and the system uses VSC as the driving voltage, VSC = 1.2 V or more, that is, the clock only during the period from t11 to t7. In the charging period, the time required for the clock to start moving is long, and in the discharging period, the time required for the clock to stop is short, resulting in a clock that is not desirable for the user.
Note that VON (0.4 V) is a voltage B at which startup is performed for triple boosting.
Therefore, the condition of VON × 3 ≧ Vup is set as follows.
It is obvious. VLim (2.3 V ) is set to 2.3 V with a margin, since the withstand voltage of the capacitor 3 used in the present embodiment was 2.4 V.

Here, the switching of the boosting ratio is performed between VSS and Vup, Vup.
This is done by comparing down, but this has the following effects
There is . In the present invention, there are three detection voltages contributing to the switching of the boosting ratio. Immediate start ← → VON of the triple boosting and Vup and Vdown described above.
In the case of a system that performs the detection by the voltage detection, four detection voltages are required. That is, immediately start ← → 3 times boost, 3
Double boost ← → double boost, double boost ← → 1.5 boost,
The detection voltage must be set at four switching points of 5 × boost →→ 1 × boost. Vss always boosts VSC is Vup
(1.2V) or more, it is necessary to provide a detection voltage as follows.

Immediate start ← → 3 times boost ・ ・ ・ 0.4V 3 times boost ← → 2 times boost ・ ・ ・ 0.6V 2 times boost ← → 1.5 times boost ・ ・ ・ 0.8V 1.5 times Step-up ← → one-time step-up... 1.2 V As described above, in the present invention, the detection voltage can be reduced by one, and the chip area of the IC can be reduced. Further, even when the minimum operating voltage of the watch body is changed due to design or process reasons, the present invention also provides that VON
Although only two detection voltage values (0.4 V) and Vup ( 1.2 V ) need to be changed, four detection voltages need to be changed in a system in which boost switching is performed by VSC detection. That is,
To adjust the detection voltage by taking out the detection voltage adjustment terminal from the IC, many adjustment terminals are required.
According to the present invention, the number of adjustment terminals can be reduced,
An increase in the IC chip area can be prevented. Further, the present invention is a four-valued multi-stage booster circuit, but if the number of booster capacitors 8.9 is increased from three to three, an eight-value booster can be set. That is, 1 times, ¹ _1/3-fold, 1.5-fold, 1
_^2/3-fold, 2-fold, 2.5-fold, 3-fold, an 8 value of 4 times,
In the boosting magnification switching system based on VSC detection, it is necessary to provide a detection voltage for all of the above, but in the present invention, the detection voltage may be the same. As described above, according to the present invention, the system up of the boosting circuit can be easily performed.

Next, a specific configuration of the multi-stage booster circuit 7 is shown in FIG.
Shown in Tr1 to Tr7 are F for capacitor reconnection
ET, and ON / OFF of this FET is controlled by a boosting clock of 1 KHz. A dashed-line block 32 is a known up-down counter, and holds a 4-value boost ratio by a combination of its 2-bit outputs SA and SB. FIG. 11 shows the relationship between SA and SB and the boost ratio. Mup input to the up / down counter 32
Is a signal output from the VSS detection circuit 11, and
A clock pulse is output when the voltage falls below up (1.2 V), and "0" is active . Similarly, Mdown is V
Clock that SS is output when exceeding the Vdown (2.0V)
It is a pulse . As described above, the boosting ratio is switched by the output of the VSS detection circuit 11. Hereinafter, the expression “0” or “1” is used to describe the logic signal, and “0” or “1” is used.
Is the minus side (VSS side) of the auxiliary capacitor 10,
“1” indicates the + side (VDD side) of the auxiliary capacitor 10. Reference numeral 33 denotes a boost reference signal generating circuit which outputs CL1 and CL2 as boost reference signals based on the standard signals φ1K and φ2KM output in a divided cycle. Reference numeral 34 denotes a switching control circuit that outputs the above CL1 and CL2. Reference numeral 34 denotes a switching control circuit,
2 and a signal decoded from SA and SB is output.
The switching of one Tr7 is controlled. The above circuit operation is shown in the timing chart for each boost ratio.
Is 12, that shown in condenser connected equivalent diagram for each step-up factor is 13. In FIG. 12, Trn
Means that Trn is turned on when becomes 1.
FIG. 12A shows a switching control signal at the time of 1-time boosting, and Tr1, 3, 4, 5, and 7 are always on. At this time, the capacitor equivalent circuit becomes as shown in FIG.
All the capacitors 9 and 10 are connected in parallel, and the voltage VSC of the capacitor 3 and the voltage VSC of the auxiliary capacitor 10 are
SS becomes equal. FIG. 12B shows a switching control signal at the time of 1.5-times boosting. In the section of FIG.
3,6 are turned on, and Tr2,4,5,7 are turned on in the section (b). FIG. 13B shows a capacitor equivalent circuit at the time of 1.5-times boosting. In the section (a), the boost capacitors 8 and 9 are charged with 0.5 × VSC, respectively, and in the section (b), VSC is charged.
The auxiliary capacitor 10 is charged with 1.5 × VSC which is the sum of the above and 0.5 × VSC. Similarly, (C) of FIG. 12 and FIG. 13 show the case of double boosting, and Tr1, 3, 5, 7 in the section (a).
Is turned on, and Tr2, 4, 5, 7 are turned on in the section (b), and as a result, the auxiliary capacitor 110 is charged with 2 × VSC.
(D) is a triple boost, and the section (A) is TrI, 3,
5 and 7 are turned on, and Tr2, 4, and 6 are turned on in the section (b), and as a result, the auxiliary capacitor 10 is charged with 3 × VSC.

The signal "OFF" in FIG.
In the condition of VON (0.4 V), that is, in the case of the immediate start state, it becomes 1 and at that time, the output of the boost reference signal generating circuit 33 is stopped, and all of the transistors Tr1 to Tr7 are turned off, and no boost is performed. . The outputs SA and SB of the up / down counter 32 are both initially set to 1, so that when the start is immediately released, the operation starts from triple boosting.

FIG. 14 shows a specific example of the VSS detection circuit. S
P1.2 and SP2.0 are sampling signals. When "1", the circuit is activated, and when "0", the circuit state is fixed so that no current is consumed. The portion 35 within the broken line is a known constant voltage circuit, and its output voltage is represented as VREG. 36 is VS
Reference numeral 37 denotes a resistor for detecting S, and reference numeral 37 denotes a resistor for generating a reference voltage. The respective intermediate taps are as follows: when VSS = 1.2V, VM = VREG- (r1 / r1 +
r2 + r3) When VSS = 2.0V, VM = VREG (r1 + r2 / r
(10r2 + r3). Reference numeral 38 denotes a transmission gate which detects when 1.2 V of VSS is detected.
The detection voltage is switched between when 0V is detected. 3
Reference numeral 9 denotes a comparator, which compares the vertical relationship between VSS and the detected voltage. 40 is a master latch with R1.2
, The output of the comparator 39 is latched. Similarly, 41 is also a master latch with R2.0,
The output of the comparator 39 is latched. Reference numeral 42 denotes a known differentiating circuit which outputs a Mup or Mdown clock pulse when the contents of the master latches 40 and 41 change, and changes the contents of the up / down counter 32 in FIG. φ8, φ64 and φ128 are reference signals output from the frequency divider, and φ8 is the master latches 40 and 41 and the differentiation circuit 42 for the next sampling.
There is to initialize. FIG. 15 shows a timing chart, and the above operation will be described. VSS> 2.0 in the first half
The second half is a chart when VSS <1.2V. R2.0, SP2.0, R1.2, SP1.2
Is output once every two seconds from a sampling signal generation circuit described later. When VSS> 2.0V, Mdown is output to lower the boosting ratio by one stage, and when VSS <1.2V, Mup is output to output the boosting ratio by one stage.

Next, the immediate start circuit will be described. The purpose is to make it possible to smoothly and surely shift to the boosting operation at the transition point where VSC becomes 0.4 V or less from 0.4 V or less. At the transition point, boosting needs to start, but in order for boosting to start, the oscillation circuit must be oscillating and the circuit must be operating. But,
Since the voltage at the transition point is as low as 0.4 V and the voltage is not boosted until the transition point, the circuit cannot operate. Further, if the transition point is set to a circuit operable voltage, there is no point in introducing a booster system. In order to solve the above problems, the immediate start circuit makes it possible to raise the VSS voltage at the transition point by a method different from that of the booster circuit. The specific circuit configuration is shown in FIG. VSC <VON (0.4
V), the “off” signal is 1
And the short-circuit Tr15 is turned off. In addition, initialization of the booster circuit in FIG. 10 is performed by the off signal, and all of Tr1 to Tr7 are turned off. When the generator operates in this state, the charging current i flows through the capacitor 3, and at that time, the series resistor 16 has the resistance value x i =
A voltage drop of v occurs. That is, the voltage of v + VSC is applied across the auxiliary capacitor 10 only when i is flowing. Although Tr3 and Tr4 are off at the time of immediate start, the auxiliary capacitor 10 can be charged with the voltage of v + VSC by the parasitic diode 43. The auxiliary capacitor 10 also serves as a smoothing capacitor. Thereafter, if the auxiliary capacitor 10 is charged with v + VSC, the circuit operation becomes possible. Series resistance 16
May be set so that the resistance value × i = v becomes VON ( 0.4 V ) or more. Also, the "off" signal is "1" even when the oscillation is stopped and the circuit is not operating.
Is set on the circuit so that there is no problem with starting the immediate start circuit. Further, when VSC exceeds VON and the boost operation starts, the short-circuit Tr15 is turned on, and the power generation coil 1, the rectifier diode 2, the capacitor 3
The charging efficiency is enhanced by preventing an extra impedance component from being provided in the charging path formed by the above. Also VSC
Rise above the transition point means that the generator also operates and the charging current is flowing, so it is possible to immediately start the operation, that is, raise the voltage of VSS at the transition point. . Therefore, according to the present invention, the circuit system operates at the transition point, and it is possible to smoothly and surely shift to the boosting operation. In addition, the instant start circuit of the present invention reliably operates the clock when the generator is operating, so that the clock operation can be easily monitored even when the capacitor voltage is 0.4 V or less. That is,
It is very effective for checking the operation at the time of shipment from the factory and promoting sales at stores.

FIG. 17 shows a sampling signal generation circuit for detecting four types of voltages in the present invention. 4
The types of voltage detection are Vup,
This refers to Vdown detection and VON and VLim detection in the VSC detection circuit 6. φ256M, φ1 / 2, φ64, φ128
M, φ16, and φ32 are reference signals output from the frequency divider, respectively, and generate these sampling pulses by decoding them. R2.0, R1.2, RLIM
, R0.4 are latched signals of each comparator.
SP2.0, SPI.2, SPLIM and SP0.4 are signals for operating each detection circuit. FIG. 18 shows a time chart illustrating the generation process. Here, when the sampling pulse order, particularly when VSS reaches Vdown (2.0 V), the detection sampling signal SP2.0 for lowering the boosting factor by one stage and VSC reach VON (0.4 V). Sometimes, the detection sampling signal SP0 for starting the boosting operation.
By setting 4 in the order as in this embodiment, a great effect can be obtained. FIG. 19A shows the operation of the sampling pulse order of the present invention, and FIG. 19B shows the operation when the sampling pulse order is reversed. First, FIG.
In 9 (B), VSC is output until SP0.4a is output.
Is assumed to be immediately lower than VON (0.4 V). At the time of output of SP0.4a, VSC ≧
It is assumed that VON is set, the start is immediately released, and the state shifts to the triple boosting state. At this time, VSS drops from the voltage in the immediate start state to 1.2 V (0.4 V × 3), but drops with a certain time constant without instantaneous drop. At this time, if the VSS voltage is sufficiently high (VSS> 2.0 V) at the time of immediate start, the following problem occurs. That is, at P1, VSS starts to drop to 1.2V, and when SP2.0a is continuously output at P2, if it is still VSS> 2,0V, the triple boosting state is required at the time of immediate start release. Despite being
It will be boosted twice. Then, VSS becomes 0.4
The voltage drops to V × 2 = 0.8 V, falls below the circuit operating voltage lower limit, and the circuit stops. Therefore, when VSC is 0.
Until the battery is charged to 6 V, it is not possible to shift to a normal boosting operation, and the time from the stopped state at the time of charging the watch to the start of movement is lengthened, which is inconvenient. The reason for setting VSC = 0.6 V in the above is that even if the boost is doubled when the start is immediately released, VSS = 2 ×
This is because 0.6V = 1.2V, and the circuit operation can be ensured. Therefore, in the present embodiment in FIG. 19A, the above problem is solved as follows. According to this, the order of SP2.0 and SP0.4 is reversed from that of FIG. 19 (B), and SP0.4 is output.
2.0 The time until output is long. According to the present invention, the period is 2−0.047 = 1.953 sec, and in FIG. 19B, it is 0.047 sec.
First, when SP2.0a is output, it is still in the immediate start state and is not related to the boost ratio switching. Next, when SP0.4a is output, the start is immediately canceled and the state shifts to the triple boost state.
VSS at P1 begins to drop toward 1.2V.
Here, the period from SP0.4a to SP2.0b is 1.953se.
Since it is sufficiently long as c, SP2.0b is output. At point P2, VSS is lower than 2.0V. That is, at the time of output of SP2.0b, no detection is performed, and the boosting ratio can be maintained at 3 times. Specifically, the period from SP0.4 to the next SP2.0 may be set as follows. That is, a period longer than T (sec) obtained from ｛(i × r + VON) −VON × N｝ e × P (−T / CR) + VON × N <Vdown may be set.
Here, each symbol has the following meaning.

I: the maximum current value obtained from the AC generator r: the sum of the series resistance 16 and the internal resistance of the capacitor 3 VON: 0.4 V N: step-up magnification (N = 3 in this embodiment) C = auxiliary capacitor 10 R: Equivalent resistance value of switching Tr in the multi-stage booster circuit 7 Vdown: 2.0 V In the above equation, VSS is charged up to i × r + VON at the time of immediate start release, and VON has a time constant CR based on the voltage.
× N ( 1.2V ), which means that the VSS voltage T (sec) after the immediate start release
(2.0 V).

As described above, according to the present invention, it is possible to reliably shift from the immediate start state to the boosting operation simply by adjusting the output timing of the sampling pulses SP2.0 and SP0.4. In terms of logic, only the decoding condition of the sampling signal generation circuit in FIG. 14 is adjusted, and there is no addition. As a result, the capacitor voltage VSC, which is the purpose of introducing the booster circuit, is 0.4
If the voltage is V or more, it is possible to guarantee that the clock operation can be performed even when the generator is not operating.

[0035]

As described above, the present invention firstly
The voltage of the first power storage unit charged by the electromotive force of the electric machine is
In a relatively low state, the voltage is boosted by the booster circuit.
Boost the clock, so you can extend the operating time of the watch
You. Also, the first power storage unit is charged by the generator.That fixed
Within rated voltageOvercharge protection circuit when overcharge protection voltage is reached
Turns on, and the electromotive force of the generator does not flow into the first power storage unit
To bypassOf the first power storage unitSafety can be secured
You. In order to extend the operating time of the watch,
It is preferable that the power storage unit 1 be charged for a longer time.
According to the present invention, the ON voltage of the overcharge prevention circuit is increased by the booster circuit.
Is set higher than theTo beSo the
The first storage unit can be charged to a higher voltage, and
The operation time of the clock by the power storage unit can be extended
You. Here, the ON voltage of the overcharge prevention circuit isBy
WhatBoostedEven at the highest voltageis thereFirst reference power
PressureLess than or equalbecomeIf the generator has finished power generation
After the time point (t6 in FIG. 9), the voltage is increased when the first power storage unit is discharged.
Starting voltage levelA second reference voltage that isuntil
The time to descend (corresponding to t7 in FIG. 9) is short
On the other hand, according to the present invention, as shown by the solid line in FIG.
The on-voltage of the protection circuit is boosted by the boosterThe best doneVoltage
IsFirst reference voltageHigher thanIs set
ToSo at the time of dischargeBelow the second reference voltage
WasThe time of the start of boosting (t7 in FIG. 9) is delayed,Increase pressure early
Of the discharge current in the first power storage unit due to the increase in the magnification.
increaseThe start is delayed,From the first power storage unitTo the second power storage unit
Charging efficiency can be further improved.On the other hand,
During charging of the first power storage unit during power generation,
A circuit configured to detect the boosted voltage by the second voltage detection circuit;
That the detected voltage exceeds the first reference voltage
When this is done, the boosting ratio decreases, but the first reference
Is set lower than the ON voltage of the overcharge prevention circuit.
It is possible to lower the boost ratio early
it can. Here, when the step-up ratio is lowered, the step-up ratio
Proportionally, the discharge current from the first power storage unit to the booster circuit side also increases.
Will fall So, compared to when the boost ratio is high,
The amount of power stored in the first power storage unit increases, and accordingly, the second power storage
The amount of charge to the part also increases, so that the clock circuit can be driven
The cutting time can be lengthened.Where the overcharge
Voltage used for operation of prevention circuit and operation of the booster circuit
The detection circuit detects a voltage of the first power storage unit and detects the detected voltage.
Overcharging for preventing overcharging of the first power storage unit based on pressure
A first voltage detection circuit for outputting to a protection circuit;
The voltage of the power section is detected and the detection result is output to the booster circuit.
Is configured separately from the second voltage detection circuit
In the operation of the overcharge prevention circuit and the operation of the booster circuit
Are performed independently of each other without affecting each other.
The work is done reliably. That is,The second voltage detection circuit
Therefore, the boosted voltage is applied to the first reference voltage.
Voltage has been exceeded, or below the second reference voltage
Can be easily detected, and the first reference
The overvoltage protection circuit to a voltage at which the overcharge protection circuit is turned on.
LowIt is easy to set and fine
Adjustment also becomes easy. The overcharge prevention circuit is provided with the AC
Since it is connected between the electric machine and the full-wave rectifier circuit,
The power of the power supply is passed through the overcharge prevention circuit by this rectifier circuit.
The secondary power supply voltage
Never descend. Therefore, the boost operation operates stably.
Can be made.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of a power generation electronic wristwatch of the present invention.

FIG. 2 is a principle diagram of an AC generator.

3A is a half-wave rectification circuit diagram, and FIG. 3B is a full-wave rectification circuit diagram.

FIG. 4 is a diagram showing a generated current.

FIG. 5A is a circuit diagram showing a limiter circuit and a rectifier circuit of the present invention, and FIG. 5B is a circuit diagram showing a conventional limiter circuit and a rectifier circuit.

6A is a conventional limiter circuit using PNP-type Tr, and FIG. 6B is a conventional limiter circuit using NPN-type Tr.

7A is a limiter circuit of the present invention using PNP-type Tr, and FIG. 7B is a limiter circuit of the present invention using NPN-type Tr.

FIG. 8 is a diagram illustrating a limiter diagram of the present invention in a full-wave rectifier circuit.

FIG. 9 is a conceptual diagram of a boosting operation.

FIG. 10 is a detailed circuit diagram of a multi-stage booster circuit.

FIG. 11 is a diagram illustrating a method of storing a circuit of a boost factor.

FIG. 12 is a time chart of a multi-stage booster circuit.

FIG. 13 is a capacitor connection equivalent circuit diagram of the multi-stage booster circuit.

FIG. 14 is a detailed circuit diagram of an auxiliary capacitor voltage detection circuit.

FIG. 15 is a time chart of the circuit diagram in FIG. 14;

FIG. 16 is a detailed circuit diagram of an immediate start circuit.

FIG. 17 is a circuit diagram of a sampling signal generation circuit for voltage detection.

FIG. 18 is a time chart of a sampling signal generation circuit.

FIG. 19 is a conceptual diagram showing a transition of an auxiliary capacitor voltage at the time of immediate start release.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Generating coil 2 ... Rectifier diode 3 ... High capacity capacitor 4 ... Limiter 5 ... Backflow prevention diode 6 ... VSC detection circuit 7 ... Multi-stage booster circuit 8,9 ...・ Boost capacitor 10 ・ ・ ・ Auxiliary capacitor 11 ・ ・ ・ VSS detection circuit 12 ・ ・ ・ Clock circuit 13 ・ ・ ・ Crystal vibrator 14 ・ ・ ・ Motor coil 17 ・ ・ ・ Rotor 18 ・ ・ ・ Stator

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁷ identification code FI H02P 9/04 H02P 9/04 Z (58) Field surveyed (Int.Cl. ⁷ , DB name) G04C 10/00 G04G 1 / 00 310

Claims (3)

(57) [Claims] 1. A generator, a first power storage unit charged with electromotive force of the generator, a first voltage detection circuit for detecting a voltage of the first power storage unit, and a first voltage An overcharge prevention circuit for preventing overcharging of the first power storage unit based on a detection voltage of the detection circuit, a booster circuit for boosting the voltage of the first power storage unit, and charging by an output of the booster circuit A second power storage unit, a second voltage detection circuit that detects a voltage of the second power storage unit and outputs a detection result to the booster circuit,
A clock circuit driven by the second power storage unit,
The booster circuit is operated by the second voltage detection circuit.
The boosted voltage exceeds the first reference voltage.
Is detected, the boosting ratio decreases and the first reference
Below a second reference voltage lower than the reference voltage
Is configured to increase the boost ratio when
Ri, the on-voltage of the overcharge protection circuit of the first power storage unit
Is set within the rated voltage of the first reference.
An electronic timepiece with a power generator, wherein a sense voltage is set lower than an ON voltage of the overcharge prevention circuit . 2. The power generator according to claim 1, wherein the generator is an AC generator, and the first power storage unit is charged via a full-wave rectifier circuit that rectifies an electromotive force of the generator. An electronic timepiece with a power generating device as described in the above. 3. The electronic timepiece with a power generator according to claim 2, wherein the overcharge prevention circuit is connected between the AC generator and the rectifier circuit.