JPH09171086A - Electronic wrist watch with generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain sufficient power generation performance even with half wave rectifying by connecting in series an over charge prevention circuit to a switching element and rectifying element and connecting in parallel to a coil, constituting a generator device. SOLUTION: An over charge prevention circuit is connected in series to a generation coil 1 and consists of a limiter (switching element) 4 for over charge prevention and a rectifying diode 2. Alternating current induction voltage is generated with a generator coil 1 and rectified in half wave with a rectifying diode 2, and rectified power is charged in a high capacity capacitor 3. When the voltage of the capacitor 3 in the limiter 4 for over charge prevention reached a set voltage, the switch becomes on-state and the power generated in the generation coil is bypassed. The set voltage of the limiter is set within the range of rated voltage of the capacitor 3. The reduction of generation efficiency due to reverse current is prevented with a reverse current prevention diode 5. As the results, notwithstanding the half wave rectifying, sufficient performance of generation and storage can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has an AC power generator capable of generating an AC electromotive force in a coil by electromagnetic induction, charges a secondary power source with the generated power, and outputs a secondary circuit to a timepiece circuit. The present invention relates to a specific circuit configuration of an operating wristwatch.

[0002]

2. Description of the Related Art Conventionally, in a wristwatch using a battery, extending the battery life has been a major problem. However, the size of batteries used in small wristwatches was naturally limited. As one means for solving these problems, a solar cell is provided on a dial plate or other display surface as shown in US Pat. No. 4,653,931, and a secondary battery or a charging capacitor is provided by the solar cell. It is an electronic wrist watch that is charged and drives a clock circuit by the output of the secondary battery or the capacitor. However, in this structure, the black or blue solar cell or the dial is placed on the dial, which limits the design and is not preferable as an electronic timepiece whose design is for sale.

As another means, there is also a system in which an AC generator is provided in the timepiece and the timepiece circuit is driven by the generated power. However, in the case of AC electromotive force, a rectifier circuit is required. It was said that full-wave rectification by a diode bridge using four diodes was the most efficient rectifier circuit, but it was difficult to put four diodes in the small wristwatch base. Also, in order to keep the clock circuit running even when the generator is not operating and keep the clock circuit running, the generated power is charged to the secondary battery or capacitor, and the clock circuit is constantly driven by the output. Need to be. However, there is a limit to the operating voltage range of the clock circuit, and if the voltage of the secondary power supply (hereinafter, used as a general term for secondary batteries or capacitors) is not charged above the operating voltage range lower limit of the circuit, the clock will Did not move. In addition, if the capacity of the secondary power supply is reduced in order to shorten the charging time of the secondary power supply, the above problem can be solved to some extent. There is also the problem of being accelerated.

[0004]

Therefore, the present invention solves the above-mentioned circuit problems of a rechargeable wrist watch using an AC generator that does not impair the aesthetics of the design. As a limited configuration, an electronic wristwatch with a power generator that operates in the entire voltage range of a secondary power supply is provided.

[0005]

That is, according to the present invention, a generator for converting mechanical energy to electric energy, which comprises a rotor, a stator, a coil, and a mechanism for rotating the rotor, and an alternating current induced in the coil of the generator. In the electronic wristwatch with a power generator, which comprises a rectifier circuit for rectifying an electromotive force, a rechargeable secondary power source for storing power rectified by the rectifier circuit, and an overcharge circuit for preventing overcharge of the secondary power source, the overcharge is provided. An electronic wristwatch with a power generator, wherein the prevention circuit has a configuration in which a switching element and a rectifying element are connected in series, and the overcharge prevention circuit is connected in parallel to a coil that constitutes the power generation apparatus.

In the present invention, the rectifier circuit is composed of a diode A connected in series between the coil and the secondary power source, the overcharge prevention circuit is connected in parallel to the coil, and a switching element and a switching element are provided. The switching circuit is composed of two diodes B, and the cathode sides of the diode A and the diode B are connected to one terminal A of one of the coils constituting the power generator and the anode side of the diode B. The other end side of the secondary power source connected to the other end side of the element and the anode side of the diode A is connected to the other terminal B of the coil, respectively, to be an electronic wristwatch with a power generator.

Further, according to the present invention, at least a booster circuit for boosting the voltage of the secondary power source, an auxiliary capacitor for charging the boosted voltage, and the other end side of the secondary power source connected to the anode side of the diode A are provided. A load resistance serially inserted between the other end of the coil and the other end of the coil, the voltage of the secondary power supply is at a low level, and the operation of the booster circuit is stopped; An electronic wristwatch with a power generator provided with a charge control circuit for charging the auxiliary capacitor with the sum of the voltage generated in the load resistance and the voltage of the secondary power source when the charging current of the power generator flows to the secondary power source. Become.

The present invention further includes a first voltage detection circuit for comparing and detecting the voltage of the secondary power source and a predetermined voltage VON,
The electronic wristwatch with a power generator is provided with a resistance variable circuit that can vary the resistance value of the load resistor according to the detection result of the first voltage detection circuit 3.

Further, according to the present invention, the resistance variable circuit is a short switching element connected in parallel with the load resistor, and the first voltage detection circuit detects that the voltage of the secondary power supply is lower than VON. When the voltage of the secondary power source is higher than VON, the switching element is turned on and the switching element for short circuit is turned off. The electronic wristwatch with a power generator has circuit means for controlling the operation.

Further, according to the present invention, the booster circuit is a multistage booster circuit capable of switching boosting ratios, and has a second voltage detection circuit for comparing and detecting the voltage of the auxiliary capacitor and a predetermined voltage. The electronic wristwatch with a power generator has circuit means for controlling the switching of the boosting ratio according to the detection result of the voltage detection circuit.

Further, according to the present invention, the operations of the first voltage detection circuit and the second voltage detection circuit 2 are intermittently performed with a predetermined cycle, and the respective operations are not performed simultaneously, and the second voltage detection is always performed. The electronic wrist watch with a power generator is arranged in such a sequence that the first voltage detection circuit 3 is operated immediately after the operation of the circuit.

Further, according to the present invention, the operations of the first voltage detection circuit and the second voltage detection circuit are intermittently performed with a predetermined cycle, and the respective operations are not performed simultaneously, and the first voltage detection circuit An electronic wristwatch with a power generator in which the time difference between the operation and the next operation of the second voltage detection circuit is set to a predetermined time or more.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the present invention in more detail, it will be described below with reference to the drawings.

FIG. 1 is an overall circuit diagram of a power generating electronic wrist watch according to the present invention. Reference numeral 1 denotes a power generating coil, which generates an AC induced voltage generated by the generator at both ends of the coil. Reference numeral 2 denotes a rectifier diode for half-wave rectification of the AC induced voltage, and charges the rectified power to the high-capacity capacitor 3. Reference numeral 4 is a limiter Tr for preventing overcharging of the capacitor 3, which is turned on when the voltage VSC of the capacitor 3 (hereinafter, the voltage value of the capacitor 3 is defined as VSC) reaches a predetermined voltage VLim. It is for bypassing the generated power. The limiter setting voltage VLim is equal to or higher than the maximum value of the voltage required by the circuit system, and is set to fall within the rated voltage of the capacitor 3. Reference numeral 5 denotes a backflow prevention diode, which prevents a decrease in power generation efficiency due to an increase in the electromagnetic brake due to a reverse current, as will be described later. Reference numeral 7 denotes a multi-stage booster circuit, which switches the connection states of the booster capacitors 8 and 9, the capacitor 3, and the auxiliary capacitor 10 to charge the capacitor 3 with electric charge.
Boosting is realized by transferring to 0. Further, the multistage booster circuit 7 can switch four types of boosting ratios of 3 times, 2 times, 1.5 times, and 1 time, and the boosted voltage is charged in the auxiliary capacitor 10. The circuit operates by the voltage VSS of the auxiliary capacitor 10 (hereinafter, the voltage value of the auxiliary capacitor 10 is defined as VSS). By employing such a multi-stage booster circuit 7, the operating voltage value of the circuit system is optimized. Reference numeral 11 is a VSS detection circuit for detecting the voltage of the auxiliary capacitor 110. The reference voltage has two values of VupVdown, which has a relationship of Vup <Vdown, and VSS is Vdo.
When wn is exceeded, the boosting ratio is reduced, and when VSS is below Vup, the boosting ratio is increased, and the detection result is output to the multistage boosting circuit 7. 12 is a clock circuit, 327
It includes an oscillating circuit for driving the crystal oscillator 13 having an original vibration of 68 Hz, a frequency dividing circuit, and a motor driving circuit for driving the motor-use coil 14, and operates at the voltage VSS. The motor coil 14 is for driving a stepping motor for rotating a pointer. 15 short Tr
, And 16 series resistors form an immediate start circuit, and when VSC is lower than a predetermined voltage VON, an immediate start operation is performed, which will be described later in detail. It is the VSC detection circuit 6 that detects that VSC has reached the aforementioned VLim and VON. The above-mentioned vertical relationship with Vup and Vdown is VON <Vup <Vdown <VLim. The outline of the circuit has been described above, but thereafter, detailed operation of each unit and its effect will be described.

First, the principle of the AC generator used in this embodiment will be described with reference to FIG.

Reference numeral 15 is a means for generating a rotational torque, which is composed of a rotary weight having an eccentric center of rotation and a center of gravity. The rotational movement of the rotating means 15 is accelerated by the speed increasing train wheel 16 to rotate the rotor 17 as a power generation mechanism. The rotor 17 includes a permanent magnet 17 a, and a stator 18 is arranged so as to enclose the rotor 17. Coil 1 is magnetic core 1
It is wound around 9a, and the magnetic core 19a and the stator 18 are fixed by screws 20. By rotating this rotor 17, the coil 1

R2 + (WL) 2 N: Number of turns of coil φ: Number of magnetic flux passing through magnetic core 22a t: Time R: Resistance of coil W: Rotational speed of rotor 17 L: Inductance of coil This electromotive force is almost sin curve. It is an exchange that you have. Further, the rotor 17 and the hole of the stator 18 that encloses the rotor 17 are concentric circles, and the rotor magnet is enclosed over almost the entire circumference. As a result, the force (gravitational torque) that tends to stop at the place where the rotor is located can be minimized.

The AC voltage obtained by such an AC generator is rectified and the capacitor 3 is charged, but in the present invention, a simple half-wave rectification system having a diode configuration is used. By combining the generator of FIG. 2 and the half-wave rectification method, the same power generation efficiency as the full-wave rectification method is obtained. The reason is described below.

FIG. 3A shows a half-wave rectifier circuit, and FIG. 3B shows a conventional full-wave rectifier circuit. 1 is a generator coil, 3 is a capacitor, and 2 and 2a-d are rectifier diodes. FIG.
The half-wave rectifier circuit of A has only one diode in the charge loop, while the full-wave rectifier circuit of FIG. 3B has two diodes in the charge loop. Therefore, the voltage drop by the diode is doubled in the full-wave rectification method. Further, comparing the current waveforms of the respective methods, it becomes as shown in FIG. Reference numeral 24 is a reference line, 25 is a generated current in the conventional rectifier circuit, 26 is a generated current in the present invention, 27 is a loss due to a voltage drop in the conventional rectifier circuit, and 28 is a rectifier circuit according to the present invention. It is the loss due to the voltage drop at. The amount of electric charge stored in the power storage means is conventionally the area covered by 25 and 27, and that according to the present invention is the area covered by 26 and 28. In this area comparison, there is almost no difference, and the power storage performance is the same. The reason why there is no difference in the power storage performance even when the half-wave rectification is performed as compared with the conventional full-wave rectification will be described below. No current flows through the coil 1 during the period of being cut by half-wave rectification (indicated by 29 in FIG. 4), and therefore the brake torque applied to the rotor 17 is small, so that the rotary weight moves faster. That is, 2
The energy in the period of 9 is stored as the kinetic energy of the rotary weight and is released during power generation. Therefore 2 compared to 25
The peak value of 6 is also large. In addition, the rectification loss is advantageously reduced to two diodes and one half. As a result, despite the use of half-wave rectification, the power generation and storage performance is not worse than that of full-wave rectification.

Next, the structure of the limiter circuit is shown in FIG.
FIG. 5A shows a limiter circuit according to the present invention, and FIG. 5B shows a commonly used limiter circuit. Reference numeral 4 is a limiter Tr for bypassing the current when the limiter is activated, which is composed of a Pch MOSFET. This is because the clock IC requires low B power consumption,
Therefore, it is because the C-MOS process is used. That is, although the limiter Tr is configured inside the IC and becomes a MOSFET, it is more advantageous in terms of space efficiency and cost than providing an external element outside the IC. In the conventional method of connecting the limiter Tr4 in parallel with the capacitor 3, when the limiter Tr4 is turned on, the electric charge of the capacitor 3 is discharged through the path of the dotted line 30. The purpose of the limiter is to prevent overcharging of the capacitor 3. In the conventional example, it seems that this is fine because it discharges the extra charge of the capacitor 3, but the limiter Tr4 is turned on. If left unattended, the electric charge will be discharged more than necessary. To avoid this, always monitor the voltage value of the capacitor 3 and set VSC below VLim.
If it becomes, it is necessary to turn off the limiter Tr4 immediately. However, if the voltage detection circuit is constantly operated, the reference voltage generation circuit and the comparator circuit greatly increase the current consumption. Further, as a drawback of the conventional example, when the limiter Tr4 is turned on, a high voltage is directly applied to the capacitor 3 and a large current flows through the limiter Tr4. To prevent the destruction of Tr4, an extremely large T
The size must be r, which leads to an increase in IC size, which is a cost disadvantage. In order to solve the above problems, the limiter circuit according to the present invention has a structure shown in FIG. 5A by adding a backflow prevention diode 5. According to this, even if the limiter Tr4 is turned on, the charge of the capacitor 3 is never discharged because of the rectifying diode 2. Therefore, even after VSC becomes VLim, the fluctuation of VSC is only the charge consumption of the timepiece body, resulting in a gradual decrease curve, and it is not always necessary to operate the VSC detection circuit 6. That is, the VSC detection circuit 6 need only be driven intermittently in a sampling manner, and the increase in current consumption can be suppressed to a minimum. Further, a large current does not flow through Tr4, and there is no need to increase the Tr size more than necessary. Here, the dotted line 31 is the direction of the bypass current by the limiter, and when VSC reaches VLim, the supply current by power generation may be cut off thereafter. 52 is
It is a parasitic diode formed between the suppressor and the drain of the limiter Tr. If the backflow prevention diode 5 is not provided, even when the limiter Tr4 is off, a current flows in the direction opposite to the dotted line 31 during power generation. Then, as described in the section of the rectifier circuit, the brake torque of the generator increases, and the power generation efficiency decreases. It is a diode to prevent it, and only by adding this backflow prevention diode 5 and changing the connection position of the limiter Tr4,
It achieves the effects of low power consumption by intermittent operation of the voltage detection circuit, downsizing of the limiter Tr4, and securing of power generation performance.

The configuration of the limiter circuit according to the present invention is also effective when a bipolar Tr is used as a switching element. FIG. 6 shows a limiter circuit when a bipolar Tr is used as a switching element and there is no backflow prevention circuit. 6A shows a PNP type bipolar bipolar transistor, and FIG. 6B shows an NPN type bipolar bipolar transistor. First, FIG. 6A
In the above, even when the PNP type Tr 44 is off, the reverse current 46 (dotted line) flows through the diode 44b formed between the collector and the base and the switching control circuit 45. Here, the switching control circuit 45
In order to control the PNP-type Tr 44 to be off, the base of the PNP-type Tr 44 is set to the high potential side (PNP-type Tr 4
The same potential as the emitter of 4). Therefore, there is some current path that enables the current of the dotted line 46 to flow in the switching control circuit 45.
In this way, the reverse current 46 flows in FIG. 6A, and similarly in FIG. 6B, the diode 47a formed between the base and collector of the NPN type Tr 47 and the switching control circuit 48 are supplied with current. Reverse current 49 as a path
(Dotted line) flows. Therefore, according to FIG. 7 which is another embodiment of the present invention, the bipolar Tr 44 or 47
By configuring the backflow prevention diode 5 in series with
It becomes possible to configure a limiter circuit without cutting backflow current and lowering power generation performance.

The limiter circuit configuration of the present invention is also applicable to a full-wave rectification circuit using a diode bridge, an example of which is shown in FIG. When the induced voltage generated in the magneto coil 1 has a high potential below the coil 1 as shown in FIG. 8, the current path of the dotted line 50 is normally taken. If there is no backflow prevention diode 5 here, even if the limiter Tr 4 is off, it passes through the parasitic diode 52,
The current path of the dotted line 51 is taken, and the capacitor 3 is charged only on one side of full-wave rectification, and the charging performance is halved. Therefore, the addition of the backflow prevention diode 5 of the present invention is effective for a full-wave rectifier circuit.

Next, with reference to FIG. 9, a concrete example of the multistage boosting will be shown. The horizontal axis represents time, and the vertical axis represents the voltage VSC (dotted line) of the capacitor 3 and the voltage VSS of the auxiliary capacitor 10.
(Solid line) and are respectively shown. In addition, the above-mentioned VON,
Vup, Vdown, and VLim are set as follows.

VON = 0.4V Vup = 1.2V Vdowm = 2.0V VLim = 2.3V In the section from t0 to t6, the charging period is mainly in the state where the generator is operating, and after t6. Assuming that no power is being generated, the discharge period starts. In FIG. 9, the charging period and the discharging period are written on the same time scale, but in reality, the charging period is on the order of several minutes, and the discharging period is on the order of several days. Immediately after t0 to t1 and t10, the start state is set and will be described later. From time t1 when VSC exceeds 0.4V, VSC is increased to triple boosting state, and VSS is charged with a voltage of VSC × 3. When it is further charged, VSS reaches 2.0V at t2. Thus, the boosting factor is reduced by one step, resulting in double boosting. After that, when charging is further advanced, VSS reaches 2.0V at t3 and t4, respectively, and VSS becomes 2.0V, so that the boosting ratio is lowered by one step. That is, t1 ~
t2 is triple boosting, t2 to t3 is double boosting, t3 to t4 is 1.5 boosting, and t4 to t7 is 1 boosting. In addition, 1
At the time of double boosting, VSC = VSS and the voltage rises, but at this time, even if VSS reaches 2.0V, the boosting ratio is not changed. The voltage further rises and VSC = VSS =
At t5 to t6 when 2.3V is reached, the limiter Tr4 is set.
Is turned on so that the voltage does not rise above 2.3V. Next, in the discharge period after t6, 1.2 V becomes the switching point of the boosting ratio. That is, when the voltage drops and VSS = 1.2V, the boosting ratio is increased by one step to 1.
5 times boosting. After that, every time VSS drops below 1.2V, the boosting ratio increases by one step. Therefore, from t7
t8 is 1.5 times booster, t8 to t9 is 2 times booster, t9
t10 is triple boosting. By adopting such a boosting system, VSS, which is the driving power source of the timepiece, is VSC ≧
Under the conditions of 0 and 4 V, 1.2 V or more can be always secured, and the operation time of the timepiece has been successfully lengthened. In addition,
Vup (1.2V) is set to the minimum operating voltage of the circuit and pointer stepping motor, and if there is no step-up and the system uses VSC as the drive voltage, VSC = 1.2V or more, that is, from t11 to t7. The timepiece moves only during the period (1), the time until the timepiece starts to move during the charging period, and the time until the timepiece stops during the discharging period become short, which is not desirable for the user. Since VON (0.4V) is the voltage B that is activated for triple boosting, it is obvious to set the condition of VON × 3 ≧ Vup. Also, VLin (2.3V)
Indicates that the withstand voltage of the capacitor 3 used in this embodiment is 2.4.
Since it was V, a margin is set and it is set to 2.3V.

Here, the switching of the boosting ratio is performed by switching between VSS and Vup, V.
This is done by comparing down, but this has the following effects. In the present invention, there are three detection voltages that contribute to the switching of the boosting ratio, immediate start ← → VON of triple boosting, and Vup and Vdowm described above.
In the case of the system that detects the voltage of 4 above, four detection voltages are required. In other words, start immediately ← → boost 3 times, 3
Double boost ← → Double boost, Double boost ← → 1.5 boost, 1.
The detection voltage must be set at the four switching points of 5 times boost ← → 1 times boost. VSS which always boosted VSC is Vup
In order to secure (1.2 V) or more, it is necessary to provide the detection voltage as follows.

Immediate start ← → triple boost ・ ・ ・ 0.4V triple boost ← → double boost ・ ・ ・ 0.6V double boost ← → 1.5 boost ・ ・ ・ 0.8V 1.5 times Step-up ← → 1 time step-up ... 1.2V As described above, in the present invention, the detection voltage can be reduced by one unit and the chip area of the IC can be reduced. Furthermore, even when the minimum operating voltage of the watch body is changed due to design or process reasons, the present invention allows VON
(0.4V), Vup (0.2V) two detection voltage values can be changed, but in a system in which boost switching is performed by VSC detection, it is necessary to change four detection voltages. That is,
If you try to adjust the detection voltage by outputting the adjustment terminal for the detection voltage from the IC, many adjustment terminals are required.
According to the present invention, the number of adjusting terminals can be reduced,
It is possible to prevent an increase in the chip area of the IC. Further, although the present invention is a four-valued multistage booster circuit, an eight-valued boosting ratio can be set by increasing the booster capacitor 8.9 from two to three. That is, 1x, 11 / 3x, 2x, 2.5
There are eight values of three times, three times, and four times, and the boosting ratio switching system by VSC detection needs to be provided with the detection voltage for all of the above, but in the present invention, the detection voltage may be the same. As described above, according to the present invention, the system up of the booster circuit can be easily performed.

Next, a concrete configuration of the multistage booster circuit 7 is shown in FIG.
Shown in TrI to Tr7 are FEs for switching capacitors
It is T, and the on / off of this FET is controlled by the boosting clock of 1KHz. The broken line block 32 is a known up / down counter, and holds a four-value boosting ratio by combining SA and SB, which are 2-bit outputs. FIG. 11 shows the relationship between SA and SB and the boosting ratio. Mup input to the up / down counter 32
Is a signal output from the VSS system output circuit 11, where VSS is V
The clock pulse is output when it goes down (1.2 V), and "0" is active. Similarly, Mdown is V
This is a black-and-white pulse output when SS exceeds Vdown (2.0V). In this way, the boosting ratio is switched by the output of the VSS detection circuit 11. Hereinafter, the expression “0” or “1” is used to describe the logic signal, and “0” or “1” is used.
Is the minus side (VSS side) of the auxiliary capacitor 10,
"1" indicates the + side (VDD side) of the auxiliary capacitor 10. Reference numeral 33 is a boosting reference signal generating circuit, which outputs CLl and CL2, which are boosting reference signals, from the standard signals φ1K and φ2KM output from the frequency division. A switching control circuit 34 outputs the above CL1 and CL2. Reference numeral 34 is a switching control circuit, which is the CL1, CL
2 and outputs the signal decoded by SA and SB, and Tr1
It controls the switching of Tr7. The timing chart shows the above circuit operation for each boost ratio.
It is FIG. 12, and FIG. 13 is an equivalent diagram of the capacitor connection for each boosting ratio. In FIG. 12, Trn
It means that Trn turns on when becomes 1.
FIG. 12A shows a switching control signal at the time of boosting by a factor of 1, and Tr1, 3, 4, 5, and 7 are always on. At this time, the capacitor answering circuit becomes as shown in FIG.
All capacitors 9 and 10 are connected in parallel, the voltage VSC of the capacitor 3 and the voltage V of the auxiliary capacitor 10
SS becomes equal. FIG. 12B shows a switching control signal at the time of boosting 1.5 times. In the section (a), Tr1,
3,6 turn on, and Tr2,4,5,7 turn on in the section (b). FIG. 13B shows a capacitor equivalent circuit at the time of boosting 1.5 times. In the section (a), the boost capacitors 8 and 9 are charged with 0.5 × VSC, respectively, and in the section (b), VSC.
And 0.5 × VSC, which is 1.5 × VSC, is charged in the auxiliary capacitor 10. Similarly, (C) of FIG. 12 and FIG. 13 is at the time of double boosting, and Tr1, 3, 5, 7,
Is turned on, and Tr2,4,5,7 are turned on in the section (b), and as a result, the auxiliary capacitor 110 is charged with 2 × VSC.
In addition, (D) is at the time of triple boosting, and the section (a) is TrI, 3,
5,7 are turned on, Tr2,4,6 are turned on in the section (b), and as a result, the auxiliary capacitor 10 is charged with 3 × VSC.

The signal "OFF" in FIG. 10 is VSC≤
VON (0.4 V) condition, that is, 1 in the immediate start state, at that time, the output of the boosting reference signal creation signal 33 is stopped and all of Tr1 to 7 are turned off, so that boosting is not performed. . Further, the outputs SA and SB of the up / down counter 32 are both initially set to 1, and when the immediate start is released, the boosting is started from triple boosting.

FIG. 14 shows a concrete example of the VSS detection circuit. S
PI.2 and SP2.0 are sampling signals. When "1", the circuit operates, and when "0", the circuit state is fixed so that current is not consumed. A part 35 indicated by a broken line is a known constant voltage circuit, and its output voltage is represented by VREG. 36 is VS
Reference numeral 37 is a resistance for detecting S, and 37 is a resistance for creating a reference voltage. Each middle tap is Have been. 38 is a transmission gate, V
The detection voltage is switched when detecting 1.2V of SS and when detecting 2.0V. Reference numeral 39 denotes a comparator, which compares the vertical relationship between VSS and the detected voltage. A master latch 40 latches the output of the comparator 39 at the rising edge of R1.2. Similarly 41
Is also a master latch by R2.0, comparator 39
Output is latched. 42 is a known differentiating circuit,
When the contents of the master latches 40 and 41 change, Mup
Alternatively, the clock pulse of Mdown is output to change the contents of the up / down counter 32 in FIG.
φ8, φ64, and φ128 are reference signals output from the frequency divider, and φ8 is for initializing the master latches 40 and 41 and the differentiating circuit 42 for the next sampling. FIG. 15 shows a timing chart, and the above operation will be described. The first half is a chart when VSS> 2.0V, and the second half is a chart when VSS <1.2V.
R2.0, SP2.0, RI.2, SP1.2 are output once every 2 seconds from the sampling signal generation circuit described later. VSS>
When it is 2.0V, Mdown is output to decrease the boosting ratio by one step, and when VSS <1.2V, Mup is output and the boosting ratio is increased by one step.

Next, the immediate start circuit will be described. The purpose is to smoothly and surely shift to the boosting operation at the transition point where VSC changes from 0.4 V or less to 0.4 V or more. At the transition point, boosting needs to start, but in order for boosting to start, the oscillation circuit must be oscillating and the circuit must be operating. But,
The voltage at the transition point is as low as 0.4 V, and since the voltage has not been boosted up to the transition point, the circuit cannot operate. Further, if the transition point is set to a circuit operable voltage, there is no point in introducing a booster system. In order to solve the above problems, the immediate start circuit makes it possible to increase the VSS voltage to a high voltage at the transition point by a method different from that of the booster circuit. The specific circuit configuration is shown in FIG. By the VSC detection circuit 6, VSC <VON (0.4
V) is detected, the "off" signal is 1
Next, Tr15 for short circuit is turned off. Further, the boost signal in FIG. 10 is initialized by the off signal, and all TrI to Tr7 are turned off. When the generator operates in this state, the charging current i will flow into the capacitor 3, but at that time, the resistance value of the series resistor 16 × i =
A voltage drop of v occurs. That is, the voltage of v + VSC is applied to both ends of the auxiliary capacitor 10 only when i is flowing. Although Tr3 and Tr4 are off at the time of immediate start, the parasitic diode 43 can charge the auxiliary capacitor 10 with the voltage of v + VSC. Further, the auxiliary capacitor 10 also functions as a smoothing capacitor, and thereafter, if v + VSC is charged in the auxiliary capacitor 10, circuit operation becomes possible. Series resistance 16
The resistance value may be set so that the resistance value xi = v becomes VON (0.2V) or more. The "off" signal is "1" even when the oscillation is stopped and the circuit is not operating.
It is set on the circuit so that there is no problem in starting the immediate start circuit. Further, when VSC exceeds VON and starts boosting operation, the short-circuiting Tr15 is turned on, and the generator coil 1, the rectifying diode 2, the capacitor 3
The charging efficiency is improved by avoiding excess impedance in the charging path composed of the two. Also VSC
The fact that the voltage rises and exceeds the transition point means that the generator is also operating and the charging current is flowing, so it is possible to increase the VSS voltage at the immediate start operation, that is, the transition point. . Therefore, according to the present invention, the circuit system is operating at the transition point, and it is possible to smoothly and surely shift to the boosting operation. Further, the instant start circuit of the present invention ensures that the timepiece operates when the generator is operating, so that the timepiece operation can be easily monitored even when the capacitor voltage is 0.4 V or less. That is,
It is very effective for checking the operation at the time of factory shipment and PR for sales at the store.

FIG. 17 shows a sampling signal generation circuit for carrying out four types of voltage detection in the present invention. Four
The types of voltage detection are Vup in the VSS detection circuit 11,
It means Vdown detection and VON, VLim detection in the VSC detection circuit 6. φ256M, φ1 / 2, φ64, φ128
M, φ16, and φ32 are reference signals output from the frequency divider, respectively, and by decoding these, each sampling pulse is generated. R2.0, R1.2, RLIM
, R0.4 are the latch capture signals of each comparator,
SP2.0, SPI.2, SPLIM and SP0.4 are signals for operating each detection circuit. FIG. 18 shows a time chart showing the generation process. Here, when the sampling pulse order, especially VSS reaches Vdown (2.0V), the detected sampling signal SP2.0 for lowering the boosting ratio by one step and VSC reach VON (0.4V). Sometimes, the detection sampling signal SP0.
A large effect can be obtained by setting 4 in the order as in this embodiment. 19A shows the operation of the sampling pulse order of the present invention, and FIG. 19B shows the operation when the sampling pulse order is reversed. First, FIG.
In 9 (B), until V0.4a is output, VSC
Is lower than VON (0.4V) and it is assumed that the vehicle was in a start state immediately. Then, when SP0.4a is output, VSC ≧
It is assumed that VON is turned on, the immediate start is released, and the state shifts to the triple boosting state. At this time, VSS drops from the voltage in the immediate start state to 1.2 V (0.4 V × 3), but it does not drop instantaneously but drops with a certain time constant. At this time, if the VSS voltage is at a high level (VSS> 2.0V) at the time of immediate start, the following problems occur. That is, VSS starts to drop to 1.2V at P1, and if SP2.0a is output continuously at P2, and if VSS> 2,0V is still present, it is originally triple boosted when the start is released. Despite being there
The voltage will be doubled. Then VSS is 0.4
The voltage drops to V × 2 = 0.8V, falls below the lower limit of the circuit operating voltage, and the circuit stops. Therefore, VSC is 0.
Until the battery is charged to 6V, the normal boosting operation cannot be performed, and the time from the stopped state to the start of movement at the time of charging the watch is long, which is inconvenient. In the above description, VSC = 0.6V means that VSS = 2 × even if the voltage doubles when the start is canceled immediately.
This is because 0.6V = 1.2V and the circuit operation can be secured. Therefore, in the present embodiment shown in FIG. 19 (A), the above problem is solved as follows. According to this, the order of SP2.0 and SP0.4 is reversed from that of FIG. 19 (B), and SP00.4 is output.
It takes a long time until P2.0 is output. According to the present invention, the period is 2-0.047 = 1.953 sec, which is 0.047 sec in FIG. 19 (B).
First, when SP2.0a is output, it is still in an immediate start state, regardless of boost ratio switching. Then, when SP0.4a is output, it immediately cancels start and shifts to the triple boost state.
VSS at P1 begins to drop towards 1.2V.
Here, the period from SP0.4a to SP2.0b is 1.953se.
Since it is sufficiently long as c, VSS at SP2b output point P2 is below 2.0V. That is, when SP2.0b is output, detection is not performed and the boosting ratio can be kept at 3 times. Specifically, the period from SP0.4 to the next SP2.0 may be set as follows. That is, It suffices to set a period that is longer than T (sec) that is obtained more.
Here, each symbol has the following meaning.

I: Maximum current value obtained from AC generator r: Sum of series resistance 16 and internal resistance of capacitor 3 VON: 0.4V N: Boosting ratio (N = 3 in this embodiment) C = Auxiliary capacitor 10 Value R: Equivalent resistance value of switching Tr in multi-stage booster circuit Vdown: 2.0V In the above equation, VSS is charged up to i × r + VON at the time of immediate start release, and VON has a time constant CR from that voltage.
It means that the voltage drops to × N (0.2V), and the VSS voltage after T (sec) from the instant when the start is released is Vdown.
It is an expression on condition that it is lower than (2.0 V).

As described above, according to the present invention, only by adjusting the output timings of the sampling pulses SP2.0 and SP0.4, it is possible to reliably shift from the immediate start state to the boosting operation. In terms of logic, only the decoding condition of the sampling signal generation circuit of FIG. 14 is adjusted, and nothing is added. As a result, the capacitor voltage VSC, which is the purpose of introducing the booster circuit, is 0.4
If V or more, it is possible to guarantee that the clock can be operated even if the generator is not operating.

[0034]

As described above, according to the present invention, sufficient power generation performance can be obtained even with half-wave rectification, and the number of diodes can be greatly reduced from 4 to 1 of the diode bridge type. It is effective in terms of efficiency and cost.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of a power generation electronic wrist watch of the present invention.

FIG. 2 is a principle diagram of an AC generator.

3A is a half-wave rectifier circuit diagram, and FIG. 3B is a full-wave rectifier circuit diagram.

FIG. 4 is a diagram showing a generated current.

5A is a circuit diagram showing a limiter circuit and a rectifying circuit of the present invention, and FIG. 5B is a circuit diagram showing a conventional limiter circuit and a rectifying circuit.

FIG. 6A is a conventional limiter circuit using a PNP type Tr, and FIG. 6B is a conventional limiter circuit using an NPN type Tr.

FIG. 7A is a limiter circuit of the present invention using PNP type Tr, and FIG. 7B is a limiter circuit of the present invention using NPN type Tr.

FIG. 8 is a limiter circuit diagram of the main engine in a full-wave rectifier circuit.

FIG. 9 is a conceptual diagram of boosting operation.

FIG. 10 is a detailed circuit diagram of a multistage booster circuit.

FIG. 11 is a diagram showing a circuit storing method of a boosting ratio.

FIG. 12 is a time chart of a multistage booster circuit.

FIG. 13 is a capacitor connection equivalent circuit diagram of a multistage booster circuit.

FIG. 14 is a detailed circuit diagram of an auxiliary capacitor voltage detection circuit.

15 is a time chart of the circuit diagram in FIG.

FIG. 16 is a detailed circuit diagram of an immediate start circuit.

FIG. 17 is a circuit diagram of a sampling signal generation circuit for voltage detection.

FIG. 18 is a time chart of a sampling signal generation circuit.

FIG. 19 is a conceptual diagram showing the transition of the auxiliary capacitor voltage when the immediate start is released.

[Explanation of symbols]

 1 ... Generator coil 2 ... Rectifier diode 3 ... High-capacity capacitor 4 ... Limiter 5 ... Reverse current prevention diode 6 ... VSC detection circuit 7 ... Multistage booster circuit 8, 9 ...・ Boosting capacitor 10 ・ ・ ・ Auxiliary capacitor 11 ・ ・ ・ VSS detection circuit 12 ・ ・ ・ Clock circuit 13 ・ ・ ・ Crystal oscillator 14 ・ ・ ・ Motor coil 17 ・ ・ ・ Rotor 18 ・ ・ ・ Stator

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 5, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of Invention] Electronic wrist watch with power generator

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has an AC power generator capable of generating an AC electromotive force in a coil by electromagnetic induction, charges a secondary power source with the generated power, and outputs a secondary circuit to a timepiece circuit. The present invention relates to a specific circuit configuration of an operating wristwatch.

[0002]

In the Conventional from using a battery watch, and a child long battery life was big problem. However, the size of batteries used in small wristwatches was naturally limited. As one means for solving these problems, a solar cell is provided on a dial plate or other display surface as shown in US Pat. No. 4,653,931, and a secondary battery or a charging capacitor is provided by the solar cell. It is an electronic wrist watch that is charged and drives a clock circuit by the output of the secondary battery or the capacitor. However, in this arrangement would be to provide a design specific limitation for solar cells of the black or blue is disposed on the dial, were not preferred as an electronic timepiece shall sell design.

As another means, there is also a system in which an AC generator is provided in the timepiece and the timepiece circuit is driven by the generated power. However, in the case of AC electromotive force, a rectifier circuit is required. Its rectifier circuit had been four Ke diode full-wave rectifier is most efficient by a diode bridge with a good, it is difficult to put a diode 4 Ke in a small watch the scan pace. Also, in order to keep the clock circuit running even when the generator is not operating and keep the clock circuit running, the generated power is charged to the secondary battery or capacitor, and the clock circuit is constantly driven by the output. Need to be. However, there is a limit to the operating voltage range of the clock circuit, and if the voltage of the secondary power supply (hereinafter, used as a general term for secondary batteries or capacitors) is not charged above the operating voltage range lower limit of the circuit, the clock will Did not move. In addition, if the capacity of the secondary power supply is reduced in order to shorten the charging time of the secondary power supply, the above problem can be solved to some extent. There is also the problem of being accelerated.

[0004]

Therefore, the present invention solves the above-mentioned circuit problems of a rechargeable wrist watch using an AC generator that does not impair the aesthetics of the design. As a limited configuration, an electronic wristwatch with a power generator that operates in the entire voltage range of a secondary power supply is provided.

[0005]

That is, according to the present invention, a generator for converting mechanical energy to electric energy, which comprises a rotor, a stator, a coil, and a mechanism for rotating the rotor, and an alternating current induced in the coil of the generator. In the electronic wristwatch with a power generator, which comprises a rectifier circuit for rectifying an electromotive force, a rechargeable secondary power source for storing power rectified by the rectifier circuit, and an overcharge circuit for preventing overcharge of the secondary power source, the overcharge is provided. An electronic wristwatch with a power generator, wherein the prevention circuit has a configuration in which a switching element and a rectifying element are connected in series, and the overcharge prevention circuit is connected in parallel to a coil that constitutes the power generation apparatus.

In the present invention, the rectifier circuit is composed of a diode A connected in series between the coil and the secondary power source, the overcharge prevention circuit is connected in parallel to the coil, and a switching element and a switching element are provided. The switching circuit is composed of two diodes B, and the cathode sides of the diode A and the diode B are connected to one terminal A of one of the coils constituting the power generator and the anode side of the diode B. The other end side of the secondary power source connected to the other end side of the element and the anode side of the diode A is connected to the other terminal B of the coil, respectively, to be an electronic wristwatch with a power generator.

Further, according to the present invention, at least a booster circuit for boosting the voltage of the secondary power source, an auxiliary capacitor for charging the boosted voltage, and the other end side of the secondary power source connected to the anode side of the diode A are provided. A load resistance serially inserted between the other end of the coil and the other end of the coil, the voltage of the secondary power supply is at a low level, and the operation of the booster circuit is stopped; An electronic wristwatch with a power generator provided with a charge control circuit for charging the auxiliary capacitor with the sum of the voltage generated in the load resistance and the voltage of the secondary power source when the charging current of the power generator flows to the secondary power source. Become.

The present invention further includes a first voltage detection circuit for comparing and detecting the voltage of the secondary power source and a predetermined voltage VON,
The electronic wristwatch with a power generator is provided with a resistance variable circuit that can vary the resistance value of the load resistor according to the detection result of the first voltage detection circuit 3.

Further, according to the present invention, the resistance variable circuit is a short switching element connected in parallel with the load resistor, and the first voltage detection circuit detects that the voltage of the secondary power supply is lower than VON. When the voltage of the secondary power source is higher than VON, the switching element is turned on and the switching element for short circuit is turned off. The electronic wristwatch with a power generator has circuit means for controlling the operation.

Further, according to the present invention, the booster circuit is a multistage booster circuit capable of switching boosting ratios, and has a second voltage detection circuit for comparing and detecting the voltage of the auxiliary capacitor and a predetermined voltage. The electronic wristwatch with a power generator has circuit means for controlling the switching of the boosting ratio according to the detection result of the voltage detection circuit.

Further, according to the present invention, the operations of the first voltage detection circuit and the second voltage detection circuit 2 are intermittently performed with a predetermined cycle, and the respective operations are not performed simultaneously, and the second voltage detection is always performed. The electronic wrist watch with a power generator is arranged in such a sequence that the first voltage detection circuit 3 is operated immediately after the operation of the circuit.

Further, according to the present invention, the operations of the first voltage detection circuit and the second voltage detection circuit are intermittently performed with a predetermined cycle, and the respective operations are not performed simultaneously, and the first voltage detection circuit An electronic wristwatch with a power generator in which the time difference between the operation and the next operation of the second voltage detection circuit is set to a predetermined time or more.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the present invention in more detail, it will be described below with reference to the drawings.

[0014] Figure 1 is an overall circuit diagram of the generator with electronic wristwatch of the present invention. Reference numeral 1 denotes a power generating coil, which generates an AC induced voltage generated by the generator at both ends of the coil. Reference numeral 2 denotes a rectifier diode for half-wave rectification of the AC induced voltage, and charges the rectified power to the high-capacity capacitor 3. Reference numeral 4 is a limiter Tr for preventing overcharging of the capacitor 3, which is turned on when the voltage VSC of the capacitor 3 (hereinafter, the voltage value of the capacitor 3 is defined as VSC) reaches a predetermined voltage VLim. It is for bypassing the generated power. The limiter setting voltage VLim is greater than or equal to the maximum value of the voltage required by the circuit system, and the capacitor 3
It is set to fall within the rated voltage of. 5
Is a backflow prevention diode, which prevents a decrease in power generation efficiency due to an increase in an electromagnetic brake due to a reverse current, which will be described later. Reference numeral 7 denotes a multi-stage booster circuit, which switches the connection states of the booster capacitors 8 and 9, the capacitor 3, and the auxiliary capacitor 10 to transfer the charge of the capacitor 3 to the auxiliary capacitor 10 to realize boosting.
Further, the multistage booster circuit 7 can switch four types of boosting ratios of 3 times, 2 times, 1.5 times, and 1 time, and the boosted voltage is charged in the auxiliary capacitor 10. The circuit operates by the voltage VSS of the auxiliary capacitor 10 (hereinafter, the voltage value of the auxiliary capacitor 10 is defined as VSS). By employing such a multi-stage booster circuit 7, the operating voltage value of the circuit system is optimized. 11 is a VSS detection circuit for detecting the voltage of the auxiliary capacitor one 10, the reference voltage, with Vup <Vdown the relationship, there are two values Vu p and V down, VSS is V
The detection result is output to the multi-stage booster circuit 7 such that if the voltage exceeds down, the boosting ratio is reduced, and if VSS is lower than Vup, the boosting ratio is increased. 12 is a clock circuit, 32
It includes an oscillating circuit for driving the crystal oscillator 13 having an original vibration of 768 Hz, a frequency dividing circuit, and a motor driving circuit for driving the motor coil 14 and operates at the voltage VSS.
The motor coil 14 is for driving a stepping motor for rotating a pointer. 15 short T
An immediate start circuit is configured by r and 16 series resistors, and when VSC is lower than a predetermined voltage VON, an immediate start operation is performed, which will be described later in detail. It is the VSC detection circuit 6 that detects that VSC has reached the aforementioned VLim and VON. The above-mentioned vertical relationship with Vup and Vdown is VON <Vup <Vdown <VLim. The outline of the circuit has been described above, but thereafter, detailed operation of each unit and its effect will be described.

First, the principle of the AC generator used in this embodiment will be described with reference to FIG.

Reference numeral 15 is a means for generating a rotational torque, which is composed of a rotary weight having an eccentric center of rotation and a center of gravity. The rotational movement of the rotating means 15 is accelerated by the speed increasing train wheel 16 to rotate the rotor 17 as a power generation mechanism. The rotor 17 includes a permanent magnet 17 a, and a stator 18 is arranged so as to enclose the rotor 17. Coil 1 is magnetic core 1
It is wound around 9a, and the magnetic core 19a and the stator 18 are fixed by screws 20. When the rotor 17 rotates, an electromotive force represented by e = N (dφ / dt) is generated in the coil 1 i = e / (R ² + (W
An electric current of L) ² ) is generated.

N: Number of turns of coil φ: Number of magnetic flux passing through magnetic core 22a t: Time R: Resistance of coil W: Rotational speed of rotor 17 L: Inductance of coil This electromotive force is an AC having a sin curve. Further, the rotor 17 and the hole of the stator 18 that encloses the rotor 17 are concentric circles, and the rotor magnet is enclosed over almost the entire circumference. As a result, the force (gravitational torque) that tends to stop at the place where the rotor is located can be minimized.

The AC voltage obtained by such an AC generator is rectified and the capacitor 3 is charged, but in the present invention, a simple half-wave rectification system having a diode configuration is used. By combining the generator of FIG. 2 and the half-wave rectification method, the same power generation efficiency as the full-wave rectification method is obtained. The reason is described below.

FIG. 3A shows a half-wave rectifier circuit, and FIG. 3B shows a conventional full-wave rectifier circuit. 1 is a generator coil, 3 is a capacitor, and 2 and 2a-d are rectifier diodes. FIG.
The half-wave rectifier circuit of A has only one diode in the charge loop, while the full-wave rectifier circuit of FIG. 3B has two diodes in the charge loop. Therefore, the voltage drop by the diode is doubled in the full-wave rectification method. Further, comparing the current waveforms of the respective methods, it becomes as shown in FIG. Reference numeral 24 is a reference line, 25 is a generated current in the conventional rectifier circuit, 26 is a generated current in the present invention, 27 is a loss due to a voltage drop in the conventional rectifier circuit, and 28 is a rectifier circuit according to the present invention. It is the loss due to the voltage drop at. The amount of electric charge stored in the power storage means is conventionally the area covered by 25 and 27, and that according to the present invention is the area covered by 26 and 28. In this area comparison, there is almost no difference, and the power storage performance is the same. The reason why there is no difference in the power storage performance even when the half-wave rectification is performed as compared with the conventional full-wave rectification will be described below. No current flows through the coil 1 during the period of being cut by half-wave rectification (indicated by 29 in FIG. 4), and therefore the brake torque applied to the rotor 17 is small, so that the rotary weight moves faster. That is, 2
The energy in the period of 9 is stored as the kinetic energy of the rotary weight and is released during power generation. Therefore 2 compared to 25
The peak value of 6 is also large. In addition, the rectification loss is advantageously reduced to two diodes and one half. As a result, despite the use of half-wave rectification, the power generation and storage performance is not worse than that of full-wave rectification.

Next, the structure of the limiter circuit is shown in FIG.
FIG. 5A shows a limiter circuit according to the present invention, and FIG. 5B shows a commonly used limiter circuit. Reference numeral 4 is a limiter Tr for bypassing the current when the limiter is activated, which is composed of a Pch MOSFET. This is because the clock IC requires low B power consumption,
Therefore, it is because the C-MOS process is used. That is, although the limiter Tr is configured inside the IC and becomes a MOSFET, it is more advantageous in terms of space efficiency and cost than providing an external element outside the IC. In the conventional method of connecting the limiter Tr4 in parallel with the capacitor 3, when the limiter Tr4 is turned on, the electric charge of the capacitor 3 is discharged through the path of the dotted line 30. The purpose of the limiter is to prevent overcharging of the capacitor 3. In the conventional example, it seems that this is fine because it discharges the extra charge of the capacitor 3, but the limiter Tr4 is turned on. If left unattended, the electric charge will be discharged more than necessary. To avoid this, always monitor the voltage value of the capacitor 3 and set VSC below VLim.
If it becomes, it is necessary to turn off the limiter Tr4 immediately. However, if the voltage detection circuit is constantly operated, the reference voltage generation circuit and the comparator circuit greatly increase the current consumption. Further, as a drawback of the conventional example, when the limiter Tr4 is turned on, a high voltage is directly applied to the capacitor 3 and a large current flows through the limiter Tr4. To prevent the destruction of Tr4, an extremely large T
The size must be r, which leads to an increase in IC size, which is a cost disadvantage. In order to solve the above problems, the limiter circuit according to the present invention has a structure shown in FIG. 5A by adding a backflow prevention diode 5. According to this even limiter Tr4 is turned on, because of the rectifying diode 2, charge-discharge child Togamu physician of the capacitor 3. Therefore, even after VSC becomes VLim, the fluctuation of VSC is only the charge consumption of the timepiece body, resulting in a gradual decrease curve, and it is not always necessary to operate the VSC detection circuit 6. That is, the VSC detection circuit 6 need only be driven intermittently in a sampling manner, and the increase in current consumption can be suppressed to a minimum. Further, a large current does not flow through Tr4, and there is no need to increase the Tr size more than necessary. Here, the dotted line 31 is the direction of the bypass current by the limiter, and when VSC reaches VLim, the supply current by power generation may be cut off thereafter. 52 is
It is a parasitic diode formed between the suppressor and the drain of the limiter Tr. If the backflow prevention diode 5 is not provided, even when the limiter Tr4 is off, a current flows in the direction opposite to the dotted line 31 during power generation. Then, as described in the section of the rectifier circuit, the brake torque of the generator increases, and the power generation efficiency decreases. It is a diode to prevent it, and only by adding this backflow prevention diode 5 and changing the connection position of the limiter Tr4,
It achieves the effects of low power consumption by intermittent operation of the voltage detection circuit, downsizing of the limiter Tr4, and securing of power generation performance.

The configuration of the limiter circuit according to the present invention is also effective when a bipolar Tr is used as a switching element. FIG. 6 shows a limiter circuit when a bipolar Tr is used as a switching element and there is no backflow prevention circuit. 6A shows a PNP type bipolar bipolar transistor, and FIG. 6B shows an NPN type bipolar bipolar transistor. First, FIG. 6A
In the above, even when the PNP type Tr 44 is off, the reverse current 46 (dotted line) flows through the diode 44b formed between the collector and the base and the switching control circuit 45. Here, the switching control circuit 45
In order to control the PNP-type Tr 44 to be off, the base of the PNP-type Tr 44 is set to the high potential side (PNP-type Tr 4
The same potential as the emitter of 4). Therefore, there is some current path that enables the current of the dotted line 46 to flow in the switching control circuit 45.
In this way, the reverse current 46 flows in FIG. 6A, and similarly in FIG. 6B, the diode 47a formed between the base and collector of the NPN type Tr 47 and the switching control circuit 48 are supplied with current. Reverse current 49 as a path
(Dotted line) flows. Therefore, according to FIG. 7 which is another embodiment of the present invention, the bipolar Tr 44 or 47
By configuring the backflow prevention diode 5 in series with
It becomes possible to configure a limiter circuit without cutting backflow current and lowering power generation performance.

The limiter circuit configuration of the present invention is also applicable to a full-wave rectification circuit using a diode bridge, an example of which is shown in FIG. When the induced voltage generated in the magneto coil 1 has a high potential below the coil 1 as shown in FIG. 8, the current path of the dotted line 50 is normally taken. If there is no backflow prevention diode 5 here, even if the limiter Tr 4 is off, it passes through the parasitic diode 52,
The current path of the dotted line 51 is taken, and the capacitor 3 is charged only on one side of full-wave rectification, and the charging performance is halved. Therefore, the addition of the backflow prevention diode 5 of the present invention is effective for a full-wave rectifier circuit.

Next, with reference to FIG. 9, a concrete example of the multistage boosting will be shown. The horizontal axis represents time, and the vertical axis represents the voltage VSC (dotted line) of the capacitor 3 and the voltage VSS of the auxiliary capacitor 10.
(Solid line) and are respectively shown. In addition, the above-mentioned VON,
Vup, Vdown, and VLim are set as follows.

VON = 0.4V Vup = 1.2V Vdowm = 2.0V VLim = 2.3V In the section from t0 to t6, the charging period is mainly in the state where the generator is operating, and after t6. Assuming that no power is being generated, the discharge period starts. In FIG. 9, the charging period and the discharging period are written on the same time scale, but in reality, the charging period is on the order of several minutes, and the discharging period is on the order of several days. Immediately after t0 to t1 and t10, the start state is set and will be described later. From time t1 when VSC exceeds 0.4V, VSC is increased to triple boosting state, and VSS is charged with a voltage of VSC × 3. When it is further charged, VSS reaches 2.0V at t2. Thus, the boosting factor is reduced by one step, resulting in double boosting. After that, when charging is further advanced, VSS reaches 2.0V at t3 and t4, respectively, and VSS becomes 2.0V, so that the boosting ratio is lowered by one step. That is, t1 ~
t2 is triple boosting, t2 to t3 is double boosting, t3 to t4 is 1.5 boosting, and t4 to t7 is 1 boosting. In addition, 1
At the time of double boosting, VSC = VSS and the voltage rises, but at this time, even if VSS reaches 2.0V, the boosting ratio is not changed. The voltage further rises and VSC = VSS =
At t5 to t6 when 2.3V is reached, the limiter Tr4 is set.
Is turned on so that the voltage does not rise above 2.3V. Next, in the discharge period after t6, 1.2 V becomes the switching point of the boosting ratio. That is, when the voltage drops and VSS = 1.2V, the boosting ratio is increased by one step to 1.
5 times boosting. After that, every time VSS drops below 1.2V, the boosting ratio increases by one step. Therefore, from t7
t8 is 1.5 times booster, t8 to t9 is 2 times booster, t9
t10 is triple boosting. By adopting such a boosting system, VSS, which is the driving power source of the timepiece, is VSC ≧
Under the condition of 0.4V, 1.2V or more can be always secured, and the operation time of the timepiece was successfully lengthened. In addition,
Vup (1.2V) is set to the minimum operating voltage of the circuit and pointer stepping motor, and if there is no step-up and the system uses VSC as the drive voltage, VSC = 1.2V or more, that is, from t11 to t7. The timepiece moves only during the period (1), the time until the timepiece starts to move during the charging period, and the time until the timepiece stops during the discharging period become short, which is not desirable for the user. Since VON (0.4V) is the voltage B that is activated for triple boosting, it is obvious to set the condition of VON × 3 ≧ Vup. Also, VLin (2.3V)
Indicates that the withstand voltage of the capacitor 3 used in this embodiment is 2.4.
Since it was V, a margin is set and it is set to 2.3V.

Here, the switching of the boosting ratio is performed by switching between VSS and Vup, V.
This is done by comparing down, but this has the following effects. In the present invention, there are three detection voltages that contribute to the switching of the boosting ratio, immediate start ← → VON of triple boosting, and Vup and Vdowm described above.
In the case of the system that detects the voltage of 4 above, four detection voltages are required. In other words, start immediately ← → boost 3 times, 3
Double boost ← → Double boost, Double boost ← → 1.5 boost, 1.
The detection voltage must be set at the four switching points of 5 times boost ← → 1 times boost. VSS which always boosted VSC is Vup
In order to secure (1.2 V) or more, it is necessary to provide the detection voltage as follows.

Immediate start ← → triple boost ・ ・ ・ 0.4V triple boost ← → double boost ・ ・ ・ 0.6V double boost ← → 1.5 boost ・ ・ ・ 0.8V 1.5 times Step-up ← → 1 time step-up ... 1.2V As described above, in the present invention, the detection voltage can be reduced by one unit and the chip area of the IC can be reduced. Furthermore, even when the minimum operating voltage of the watch body is changed due to design or process reasons, the present invention allows VON
(0.4V), Vup (0.2V) two detection voltage values can be changed, but in a system in which boost switching is performed by VSC detection, it is necessary to change four detection voltages. That is,
If you try to adjust the detection voltage by outputting the adjustment terminal for the detection voltage from the IC, many adjustment terminals are required.
According to the present invention, the number of adjusting terminals can be reduced,
It is possible to prevent an increase in the chip area of the IC. Further, although the present invention is a four-valued multistage booster circuit, an eight-valued boosting ratio can be set by increasing the booster capacitor 8.9 from two to three. That is, 1 times, ¹ _1/3-fold, 1.5-fold, 1
_^2/3-fold, 2-fold, 2.5-fold, 3-fold, an 8 value of 4 times,
In the step-up magnification switching system by VSC detection, it is necessary to provide the detection voltage in all of the above, but in the present invention, the detection voltage may remain unchanged. As described above, according to the present invention, the system up of the booster circuit can be easily performed.

Next, a concrete configuration of the multistage booster circuit 7 is shown in FIG.
Shown in TrI to Tr7 are FEs for switching capacitors
It is T, and the on / off of this FET is controlled by the boosting clock of 1KHz. The broken line block 32 is a known up / down counter, and holds a four-value boosting ratio by combining SA and SB, which are 2-bit outputs. FIG. 11 shows the relationship between SA and SB and the boosting ratio. Mup input to the up / down counter 32
Is a signal output from the VSS system output circuit 11, where VSS is V
The clock pulse is output when it goes down (1.2 V), and "0" is active. Similarly, Mdown is V
This is a black-and-white pulse output when SS exceeds Vdown (2.0V). In this way, the boosting ratio is switched by the output of the VSS detection circuit 11. Hereinafter, the expression “0” or “1” is used to describe the logic signal, and “0” or “1” is used.
Is the minus side (VSS side) of the auxiliary capacitor 10,
"1" indicates the + side (VDD side) of the auxiliary capacitor 10. Reference numeral 33 is a boosting reference signal generating circuit, which outputs CLl and CL2, which are boosting reference signals, from the standard signals φ1K and φ2KM output from the frequency division. A switching control circuit 34 outputs the above CL1 and CL2. Reference numeral 34 is a switching control circuit, which is the CL1, CL
2 and outputs the signal decoded by SA and SB, and Tr1
It controls the switching of Tr7. The timing chart shows the above circuit operation for each boost ratio.
It is FIG. 12, and FIG. 13 is an equivalent diagram of the capacitor connection for each boosting ratio. In FIG. 12, Trn
It means that Trn turns on when becomes 1.
FIG. 12A shows a switching control signal at the time of boosting by a factor of 1, and Tr1, 3, 4, 5, and 7 are always on. At this time, the capacitor answering circuit becomes as shown in FIG.
All capacitors 9 and 10 are connected in parallel, the voltage VSC of the capacitor 3 and the voltage V of the auxiliary capacitor 10
SS becomes equal. FIG. 12B shows a switching control signal at the time of boosting 1.5 times. In the section (a), Tr1,
3,6 turn on, and Tr2,4,5,7 turn on in the section (b). FIG. 13B shows a capacitor equivalent circuit at the time of boosting 1.5 times. In the section (a), the boost capacitors 8 and 9 are charged with 0.5 × VSC, respectively, and in the section (b), VSC.
And 0.5 × VSC, which is 1.5 × VSC, is charged in the auxiliary capacitor 10. Similarly, (C) of FIG. 12 and FIG. 13 is at the time of double boosting, and Tr1, 3, 5, 7,
Is turned on, and Tr2,4,5,7 are turned on in the section (b), and as a result, the auxiliary capacitor 110 is charged with 2 × VSC.
In addition, (D) is at the time of triple boosting, and the section (a) is TrI, 3,
5,7 are turned on, Tr2,4,6 are turned on in the section (b), and as a result, the auxiliary capacitor 10 is charged with 3 × VSC.

The signal "OFF" in FIG. 10 is VSC≤
VON (0.4 V) condition, that is, 1 in the immediate start state, at that time, the output of the boosting reference signal creation signal 33 is stopped and all of Tr1 to 7 are turned off, so that boosting is not performed. . Further, the outputs SA and SB of the up / down counter 32 are both initially set to 1, and when the immediate start is released, the boosting is started from triple boosting.

FIG. 14 shows a concrete example of the VSS detection circuit. S
P1.2 and SP2.0 are sampling signals and fix the circuit state so that the circuit operates when it is "1" and the current is not consumed when it is "0". A part 35 indicated by a broken line is a known constant voltage circuit, and its output voltage is represented by VREG. 36 is VS
Reference numeral 37 is a resistance for detecting S, and 37 is a resistance for creating a reference voltage. Intermediate tap respectively, when VSS = 1.2V, when the VM = VREG chromatography (r1 / r1 + r2 tens r3) VSS = 2.0V, VM = VREG (r1 + r2 / r1 tens r2 + r3) become set as There is. Reference numeral 38 is a transmission gate, which detects when 1.2 V of VSS and 2.
The detection voltage is switched between when 0V is detected. 3
Reference numeral 9 denotes a comparator, which compares the vertical relationship between VSS and the detected voltage. 40 is a master latch R1.2
The output of the comparator 39 is latched by the rising edge of. Similarly, 41 is also a master latch by R2.0,
The output of the comparator 39 is latched. Reference numeral 42 is a known differentiating circuit, which outputs a clock pulse of Mup or Mdown when the contents of the master latches 40 and 41 change, and changes the contents of the up / down counter 32 in FIG. φ8, φ64, and φ128 are reference signals output from the frequency divider, and φ8 is the master latches 40 and 41 and the differentiation circuit 42 for the next sampling.
To initialize. FIG. 15 shows a timing chart, and the above operation will be described. VSS> 2.0 in the first half
The chart is for V, and the latter half is for VSS <1.2V. R2.0, SP2.0, R1.2, SP1.2
Is output from the sampling signal generation circuit described later once every two seconds. When VSS> 2.0V, Mdown is output to decrease the boosting ratio by one step, and when VSS <1.2V, Mup is output and the boosting ratio is increased by one step.

Next, the immediate start circuit will be described. The purpose is to smoothly and surely shift to the boosting operation at the transition point where VSC changes from 0.4 V or less to 0.4 V or more. At the transition point, boosting needs to start, but in order for boosting to start, the oscillation circuit must be oscillating and the circuit must be operating. But,
The voltage at the transition point is as low as 0.4 V, and since the voltage has not been boosted up to the transition point, the circuit cannot operate. Further, if the transition point is set to a circuit operable voltage, there is no point in introducing a booster system. In order to solve the above problems, the immediate start circuit makes it possible to increase the VSS voltage to a high voltage at the transition point by a method different from that of the booster circuit. The specific circuit configuration is shown in FIG. By the VSC detection circuit 6, VSC <VON (0.4
V) is detected, the "off" signal is 1
Next, Tr15 for short circuit is turned off. Further, the boost signal in FIG. 10 is initialized by the off signal, and all of Tr1 to Tr7 are turned off. When the generator operates in this state, the charging current i will flow into the capacitor 3, but at that time, the resistance value of the series resistor 16 × i =
A voltage drop of v occurs. That is, the voltage of v + VSC is applied to both ends of the auxiliary capacitor 10 only when i is flowing. Although Tr3 and Tr4 are off at the time of immediate start, the parasitic diode 43 can charge the auxiliary capacitor 10 with the voltage of v + VSC. Further, the auxiliary capacitor 10 also functions as a smoothing capacitor, and thereafter, if v + VSC is charged in the auxiliary capacitor 10, circuit operation becomes possible. Series resistance 16
The resistance value may be set so that the resistance value xi = v becomes VON (0.2V) or more. The "off" signal is "1" even when the oscillation is stopped and the circuit is not operating.
It is set on the circuit so that there is no problem in starting the immediate start circuit. Further, when VSC exceeds VON and starts boosting operation, the short-circuiting Tr15 is turned on, and the generator coil 1, the rectifying diode 2, the capacitor 3
The charging efficiency is improved by avoiding excess impedance in the charging path composed of the two. Also VSC
The fact that the voltage rises and exceeds the transition point means that the generator is also operating and the charging current is flowing, so it is possible to increase the VSS voltage at the immediate start operation, that is, the transition point. . Therefore, according to the present invention, the circuit system is operating at the transition point, and it is possible to smoothly and surely shift to the boosting operation. Further, the instant start circuit of the present invention ensures that the timepiece operates when the generator is operating, so that the timepiece operation can be easily monitored even when the capacitor voltage is 0.4 V or less. That is,
It is very effective for checking the operation at the time of factory shipment and PR for sales at the store.

FIG. 17 shows a sampling signal generation circuit for carrying out four types of voltage detection in the present invention. Four
The types of voltage detection are Vup in the VSS detection circuit 11,
It means Vdown detection and VON, VLim detection in the VSC detection circuit 6. φ256M, φ1 / 2, φ64, φ128
M, φ16, and φ32 are reference signals output from the frequency divider, respectively, and by decoding these, each sampling pulse is generated. R2.0, R1.2, RLIM
, R0.4 are the latch capture signals of each comparator,
SP2.0, SPI.2, SPLIM and SP0.4 are signals for operating each detection circuit. FIG. 18 shows a time chart showing the generation process. Here, when the sampling pulse order, especially VSS reaches Vdown (2.0V), the detected sampling signal SP2.0 for lowering the boosting ratio by one step and VSC reach VON (0.4V). Sometimes, the detection sampling signal SP0.
A large effect can be obtained by setting 4 in the order as in this embodiment. 19A shows the operation of the sampling pulse order of the present invention, and FIG. 19B shows the operation when the sampling pulse order is reversed. First, FIG.
In 9 (B), until V0.4a is output, VSC
Is lower than VON (0.4V) and it is assumed that the vehicle was in a start state immediately. Then, when SP0.4a is output, VSC ≧
It is assumed that VON is turned on, the immediate start is released, and the state shifts to the triple boosting state. At this time, VSS drops from the voltage in the immediate start state to 1.2 V (0.4 V × 3), but it does not drop instantaneously but drops with a certain time constant. At this time, if the VSS voltage is at a high level (VSS> 2.0V) at the time of immediate start, the following problems occur. That is, VSS starts to drop to 1.2V at P1, and if SP2.0a is output continuously at P2, and if VSS> 2,0V is still present, it is originally triple boosted when the start is released. Despite being there
The voltage will be doubled. Then VSS is 0.4
The voltage drops to V × 2 = 0.8V, falls below the lower limit of the circuit operating voltage, and the circuit stops. Therefore, VSC is 0.
Until the battery is charged to 6V, the normal boosting operation cannot be performed, and the time from the stopped state to the start of movement at the time of charging the watch is long, which is inconvenient. In the above description, VSC = 0.6V means that VSS = 2 × even if the voltage doubles when the start is canceled immediately.
This is because 0.6V = 1.2V and the circuit operation can be secured. Therefore, in the present embodiment shown in FIG. 19 (A), the above problem is solved as follows. According to this, the order of SP2.0 and SP0.4 is reversed from that of FIG. 19 (B), and SP00.4 is output.
It takes a long time until P2.0 is output. According to the present invention, the period is 2-0.047 = 1.953 sec, which is 0.047 sec in FIG. 19 (B).
First, when SP2.0a is output, it is still in an immediate start state, regardless of boost ratio switching. Then, when SP0.4a is output, it immediately cancels start and shifts to the triple boost state.
VSS at P1 begins to drop towards 1.2V.
Here, the period from SP0.4a to SP2.0b is 1.953se.
Since it is sufficiently long as c, VSS at SP2b output point P2 is below 2.0V. That is, when SP2.0b is output, detection is not performed and the boosting ratio can be kept at 3 times. Specifically, the period from SP0.4 to the next SP2.0 may be set as follows. That is, {(i × r + VON) −VON × N} e × P (−T / CR)
A period longer than T (sec) obtained by + VON × N <Vdown may be set.
Here, each symbol has the following meaning.

I: Maximum current value obtained from AC generator r: Sum of series resistance 16 and internal resistance of capacitor 3 VON: 0.4V N: Boosting ratio (N = 3 in this embodiment) C = Auxiliary capacitor 10 Value R: Equivalent resistance value of switching Tr in multi-stage booster circuit Vdown: 2.0V In the above equation, VSS is charged up to i × r + VON at the time of immediate start release, and VON has a time constant CR from that voltage.
It means that the voltage drops to × N (0.2V), and the VSS voltage after T (sec) from the instant when the start is released is Vdown.
It is an expression on condition that it is lower than (2.0 V).

As described above, according to the present invention, only by adjusting the output timings of the sampling pulses SP2.0 and SP0.4, it is possible to reliably shift from the immediate start state to the boosting operation. In terms of logic, only the decoding condition of the sampling signal generation circuit of FIG. 14 is adjusted, and nothing is added. As a result, the capacitor voltage VSC, which is the purpose of introducing the booster circuit, is 0.4
If V or more, it is possible to guarantee that the clock can be operated even if the generator is not operating.

[0034]

As described above, according to the present invention, sufficient power generation performance can be obtained even with half-wave rectification, and the number of diodes can be greatly reduced from 4 to 1 of the diode bridge type. It is effective in terms of efficiency and cost.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of a power generation electronic wrist watch of the present invention.

FIG. 2 is a principle diagram of an AC generator.

3A is a half-wave rectifier circuit diagram, and FIG. 3B is a full-wave rectifier circuit diagram.

FIG. 4 is a diagram showing a generated current.

5A is a circuit diagram showing a limiter circuit and a rectifying circuit of the present invention, and FIG. 5B is a circuit diagram showing a conventional limiter circuit and a rectifying circuit.

FIG. 6A is a conventional limiter circuit using a PNP type Tr, and FIG. 6B is a conventional limiter circuit using an NPN type Tr.

FIG. 7A is a limiter circuit of the present invention using PNP type Tr, and FIG. 7B is a limiter circuit of the present invention using NPN type Tr.

FIG. 8 is a limiter circuit diagram of the main engine in a full-wave rectifier circuit.

FIG. 9 is a conceptual diagram of boosting operation.

FIG. 10 is a detailed circuit diagram of a multistage booster circuit.

FIG. 11 is a diagram showing a circuit storing method of a boosting ratio.

FIG. 12 is a time chart of a multistage booster circuit.

FIG. 13 is a capacitor connection equivalent circuit diagram of a multistage booster circuit.

FIG. 14 is a detailed circuit diagram of an auxiliary capacitor voltage detection circuit.

15 is a time chart of the circuit diagram in FIG.

FIG. 16 is a detailed circuit diagram of an immediate start circuit.

FIG. 17 is a circuit diagram of a sampling signal generation circuit for voltage detection.

FIG. 18 is a time chart of a sampling signal generation circuit.

FIG. 19 is a conceptual diagram showing the transition of the auxiliary capacitor voltage when the immediate start is released.

[Explanation of Codes] 1 ... Generator coil 2 ... Rectifier diode 3 ... High-capacity capacitor 4 ... Limiter 5 ... Backflow prevention diode 6 ... VSC detection circuit 7 ... Multistage booster circuit 8, 9 ... Boost capacitor 10 ... Auxiliary capacitor 11 ... VSS detection circuit 12 ... Clock circuit 13 ... Crystal oscillator 14 ... Motor coil 17 ... Rotor 18 ... Stator

Claims (8)

[Claims] 1. A power generator for converting mechanical energy into electric energy, which is composed of at least a rotor, a stator, a coil, and a mechanism for rotating the rotor, and a rectifying circuit for rectifying an AC electromotive force induced in a coil of the power generator. In an electronic wristwatch with a power generator comprising a rechargeable secondary power source that stores the power rectified by the rectifier circuit and an overcharge prevention circuit that prevents overcharge of the secondary power source, the overcharge prevention circuit is a switching element. An electronic wristwatch with a power generator, wherein the rectifier element is connected in series, and the overcharge prevention circuit is connected in parallel to a coil forming the power generator. 2. The rectifier circuit includes a first diode A connected in series between the coil and the secondary power source, and the overcharge prevention circuit includes a switching element connected in parallel to the coil. The second diode B is connected, and the cathode sides of the diode A and the diode B are respectively connected to one terminal A of the coil constituting the power generator and the anode side of the diode B. The power generator according to claim 1, wherein the other end side of the switching element and the other end side of the secondary power source connected to the anode side of the diode A are connected to the other terminal B of the coil, respectively. Electronic wrist watch. 3. A booster circuit for boosting at least the voltage of the secondary power source, an auxiliary capacitor for charging the boosted voltage, the other end side of the secondary power source connected to the anode side of the diode A, and the coil. And a load resistance inserted in series with the other terminal B of the secondary power supply, the voltage of the secondary power supply is at a low level, and the operation of the booster circuit is stopped, and 7. A charge control circuit for charging the auxiliary capacitor with the sum of the voltage generated in the load resistance and the voltage of the secondary power source when the charging current of the power generator flows to the power source. An electronic wrist watch with a power generator according to 1. 4. A first voltage detection circuit for comparing and detecting a voltage of the secondary power supply and a predetermined voltage VON, and varying a resistance value of the load resistor according to a detection result of the first voltage detection circuit. An electronic wristwatch with a power generator according to claim 3, further comprising a variable resistance circuit capable of achieving the above. 5. The variable resistance circuit is a switching element for short circuit connected in parallel to the load resistor,
When the voltage detection circuit detects that the voltage of the secondary power supply is lower than VON, the switching element for short circuit is turned off and the operation of the booster circuit is stopped, and the voltage of the secondary power supply is VON. 4. The electronic wrist watch with a power generator according to claim 3, further comprising circuit means for controlling the switching element to be turned on and operating the booster circuit when it is higher. 6. The booster circuit is a multistage booster circuit capable of switching boosting ratios, and has a second voltage detection circuit for comparing and detecting a voltage of the auxiliary capacitor and a predetermined voltage, and the second voltage detection circuit. 4. The electronic wristwatch with a power generator according to claim 3, further comprising circuit means for controlling switching of the boosting ratio according to the detection result of the circuit. 7. The operations of the first voltage detection circuit and the second voltage detection circuit are intermittently performed at a predetermined cycle, and the respective operations are not simultaneously performed, and are always the second voltage detection circuit.
7. The electronic wristwatch with a power generator according to claim 6, wherein the order is such that the operation of the first voltage detection circuit is performed immediately after the operation of the voltage detection circuit. 8. The operations of the first voltage detection circuit and the second voltage detection circuit are performed intermittently at a predetermined cycle, and the respective operations are not performed simultaneously, and the operation of the first voltage detection circuit is performed. 7. The power-generating electronic wristwatch according to claim 6, wherein a time difference from the next operation of the second voltage detection circuit is set to be a predetermined time or more.