JP2004140992A - Power generation detecting circuit, electronic apparatus, and power generation detecting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make various processes performed properly for preventing adverse effects on an electronic device arising from charging, and to surely detect a state of charge, in order to lower the consumption of electric power. <P>SOLUTION: Output terminal voltages V1, V2 of a generator 101 are compared with a prescribed voltage VDD, corresponding to the terminal voltage of an electricity-storing device 104. Based on the result of these comparisons, a condition corresponding to the charged state is detected, when the output terminal voltages V1, V2 exceeds the terminal voltage VDD of the electricity-storing device. Thus, adverse effects on motor drive by electromagnetic noises generated from the generator 101, and the state of charge in which a charging current flow generates adverse effects to circuit operations due to the fluctuation of a power source voltage generated caused by the internal resistance of the electricity-storing device 104, are surely detected. Also, countermeasures on the adverse effects resulting from charging are taken, only when under charging is being made with a charge-allowing current, and by suppressing the increase in the power consumption that may be caused by excessive countermeasures, the drive period of time of the electronic device is prolonged. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a power generation detection circuit, an electronic device, and a power generation detection method, and in particular, to a power generation device and a portable electronic device having a power storage device that stores power generated by the power generation device, power generation in which a generated current can flow. The present invention relates to a power generation detection circuit, an electronic device, and a power generation detection method for detecting whether power generation has been performed.

In recent years, small electronic timepieces such as wristwatches that incorporate a power generation device such as a solar cell and operate without battery replacement have been realized. These electronic timepieces have the function of once charging the power generated by the power generator to a large-capacity capacitor, and when power is not generated, the time is displayed using the power discharged from the capacitor. ing. For this reason, stable operation is possible for a long time without batteries, and in consideration of the trouble of replacing batteries or the problem of battery disposal, it is expected that many electronic watches will have a built-in power generator in the future. ing.

On the other hand, during charging, the motor may be adversely affected by the level of electromagnetic noise generated from the generator.
Further, at the time of charging, a power supply voltage fluctuation due to the charging current also occurs due to the internal resistance of the secondary battery.
Therefore, in order to avoid such a problem, in an electronic timepiece incorporating the above-described power generation device, a power generation detection circuit is provided to detect whether or not power is being generated by the power generation device. Processing is performed assuming that the battery has been charged.

However, just because power generation is detected does not necessarily mean that the generated power contributes to charging, and it becomes possible to charge the rechargeable battery only after a power generation voltage equal to or higher than the terminal voltage of the rechargeable battery is generated. , A charging current flows. Therefore, in the detection of the absolute value of the power generation voltage, power generation that does not contribute to charging is detected, and the processing is performed more than necessary, which results in an increase in power consumption.

Accordingly, an object of the present invention is to provide a power generation detection circuit capable of reliably detecting a power generation state, appropriately performing various processes for avoiding adverse effects of electronic devices accompanying power generation, and reducing power consumption. An object of the present invention is to provide a device and a power generation detection method.
Another object of the present invention is to ensure that a state in which a bypass current flows through a bypass is ensured even when a limiter circuit that causes a generated current to flow through a bypass that bypasses a charging path to the power storage device is operating. It is an object of the present invention to detect and appropriately perform various processes for avoiding an adverse effect on electronic devices due to power generation.

In order to solve the above problems, a power generation detection circuit according to the present invention includes a power storage device that stores electric energy obtained by converting first energy in a power generation device having a pair of output terminals, and an output terminal of the power generation device. Comparison means for comparing the voltage of the power storage device with a predetermined voltage corresponding to the terminal voltage of the power storage device, and outputting a comparison result signal;
Power generation detection means for outputting a power generation detection signal corresponding to a state in which a generated current can flow when the voltage of the output terminal exceeds the terminal voltage of the power storage device based on the comparison result signal. I have.

A power generation detection circuit according to the present invention is a power generation device that is an AC power generation device having a first output terminal and a second output terminal, and is configured to generate power capable of charging a power storage device that stores electric energy obtained by converting first energy. In a power generation detection circuit for detecting whether or not the power storage device is in a state, a first output terminal voltage that is a terminal voltage of the first output terminal is compared with a predetermined voltage corresponding to a terminal voltage of the power storage device, and a first comparison is performed. First comparing means for outputting a result signal; comparing a second output terminal voltage, which is a terminal voltage of the second output terminal, with a predetermined voltage corresponding to a terminal voltage of the power storage device; And a second comparing means for outputting the first output terminal voltage or the second output terminal voltage higher than a terminal voltage of the power storage device based on the first comparison result signal and the second comparison result signal. It is characterized with the power generation detecting means for outputting a power detection signal to a state in which the generated current can flow, further comprising: a if that.

The power generation detection circuit according to the present invention is a power generation detection circuit that detects a power generation state in which a power storage device that stores electric energy obtained by converting first energy in a power generation device can be charged. A boosting power storage device connected to a terminal, a comparing unit that compares a storage voltage of the boosting power storage device with a predetermined voltage corresponding to a terminal voltage of the power storage device, and outputs a comparison result signal; Power generation detection means for outputting a power generation detection signal corresponding to a state in which a generated current can flow when the output terminal voltage exceeds a predetermined voltage corresponding to the terminal voltage of the power storage device based on a signal. Features.

{Circle around (2)} The comparing means compares a voltage obtained by offsetting one of the two input voltages by a predetermined amount with the other input voltage.

The predetermined voltage corresponding to the terminal voltage of the power storage device is a voltage obtained by adding a predetermined offset voltage to the terminal voltage of the power storage device.

Further, the power generation detecting means obtains a logical product of the first comparison result signal and the second comparison result signal and outputs the result as an original power generation detection signal. And a smoothing means for outputting as a detection signal.

Further, the power generation detection means performs an OR operation on the first comparison result signal and the second comparison result signal and outputs the result as an original power generation detection signal. And a smoothing means for outputting as a detection signal.

The power generation current is a charging current for charging the power storage device, and the power generation detection unit outputs a power generation detection signal corresponding to a state of charge when a voltage of the output terminal exceeds a terminal voltage of the power storage device. It is characterized by doing.

A charging voltage detecting unit configured to detect a charging voltage of the power storage device; a charging voltage detecting unit configured to detect a charging voltage of the power storage device; and a predetermined voltage determined by the charging voltage detecting unit. If more than, the generated current flowing from one of the input terminals through a bypass path bypassing the charging path to the power storage device, through the pair of input terminals by supplying to the other input terminal Closed-loop forming means for forming a closed loop, wherein the generated current is a bypass current flowing through the bypass circuit, and the power generation detection means performs the bypass when the output terminal voltage exceeds the terminal voltage of the power storage device. It is characterized by outputting a power generation detection signal corresponding to a state in which current can flow.

An electronic device according to an aspect of the invention includes a power generation device that converts first energy into electric energy, a power storage device that stores the electric energy, and a driven unit that is driven by the electric energy stored in the power storage device. A power generation detection circuit according to any one of claims 1 to 9.

Further, the driven means is provided with timing means for performing a timing operation.

The power generation detection method of the present invention corresponds to a voltage of an output terminal of a power generation device having a pair of output terminals and a terminal voltage of a power storage device that stores electric energy obtained by converting first energy in the power generation device. A comparison step of comparing the output terminal voltage with a predetermined voltage, and detecting that the state corresponds to a state in which a generated current can flow when the output terminal voltage exceeds the terminal voltage of the power storage device based on a result of the comparison in the comparison step. And a power generation detecting step.

The power generation detection method of the present invention is a power generation detection method for detecting a power generation state of a power generation device that is an AC power generation device having a first output terminal and a second output terminal, wherein the first output is a terminal voltage of the first output terminal. A first comparing step of comparing a terminal voltage with a predetermined voltage corresponding to a terminal voltage of a power storage device that stores electric energy obtained by converting first energy in the power generation device; and the second output. A second comparing step of comparing a second output terminal voltage, which is a terminal voltage of a terminal, with a predetermined voltage corresponding to the terminal voltage of the power storage device, and a comparison in the first comparing step and the second comparing step A power generation detection step of detecting that the first output terminal voltage or the second output terminal voltage exceeds the terminal voltage of the power storage device to correspond to a power generation state based on the result of the above. It is characterized in that was.

A power generation detection method according to the present invention is a terminal of a power storage device that stores electric energy obtained by converting first energy in a power generation device via a boosting power storage device connected to one output terminal of the power generation device. A comparing step of comparing a predetermined voltage corresponding to a voltage with a storage voltage of the boosting power storage device;
A power generation detecting step of detecting that, when the output terminal voltage exceeds a predetermined voltage corresponding to the terminal voltage of the power storage device, the state corresponds to a state in which a generated current can flow based on the result of the comparison. It is characterized by.

The comparison step is characterized in that, of the two input voltages, a voltage obtained by offsetting one of the two input voltages by a predetermined amount is compared with the other voltage.

(5) The predetermined voltage corresponding to the terminal voltage of the power storage device is set to a voltage obtained by adding a predetermined offset voltage to the terminal voltage of the power storage device.

Further, the generated current is a charging current for charging the power storage device,
The power generation detecting step is characterized in that when the voltage of the output terminal exceeds the terminal voltage of the power storage device, it is detected that the state corresponds to a power generation state.

Further, in the charging voltage detecting step of detecting the charging voltage of the power storage device, and in the charging voltage detecting step, when the detected charging voltage exceeds a predetermined voltage, power generation flowing from one of the input terminals. A closed loop forming step of forming a closed loop through a pair of the input terminals by supplying a current to the other input terminal via a bypass path bypassing a charging path to the power storage device; The current is a bypass current flowing through the bypass circuit, and the power generation detection step detects that the bypass current is in a state where the bypass current can flow when the output terminal voltage exceeds the terminal voltage of the power storage device. And

ADVANTAGE OF THE INVENTION According to this invention, the bad influence on the motor drive by the electromagnetic noise level which generate | occur | produces from a power generation part (generator), and the bad influence on the circuit operation | movement by the power supply voltage fluctuation which arises due to the internal resistance of a secondary battery are produced. It is possible to reliably detect the state of power generation in which a potential generated current flows, and to take measures against adverse effects associated with charging only during actual charging in which a chargeable current flows. , The driving time of the electronic device can be prolonged.

In addition, even when a limiter circuit or the like that causes the generated current to flow through a detour that bypasses the charging path to the power storage device is operating, the state in which the detour current flows in the detour is reliably detected, and the electronic power associated with power generation is detected. Each process for avoiding adverse effects on the device can be appropriately performed.

Next, a preferred embodiment of the present invention will be described with reference to the drawings.
[1] First Embodiment
[1.1] Overall Configuration FIG. 1 shows a schematic configuration of a timing device 1 which is an electronic device of the first embodiment.
The timekeeping device 1 is a wristwatch, and a user uses the belt connected to the device body by wrapping it around a wrist.
The timekeeping device 1 is roughly divided into a power generation unit A that generates AC power, a power supply unit B that rectifies the AC voltage from the power generation unit A and stores the boosted voltage, and supplies power to each component. A control unit C that detects the power generation state of the power generation unit A and controls the entire apparatus based on the detection result, a hand movement mechanism D that drives a pointer, and a hand movement mechanism D that is driven based on a control signal from the control unit C And a driving unit E.

In this case, the control unit C drives the hand movement mechanism D to display the time in accordance with the power generation state of the power generation unit A, and a power saving mode in which power supply to the hand movement mechanism D is stopped to save power. And to switch. The transition from the power saving mode to the display mode is forcibly made by the user holding the timepiece 1 and shaking it. Hereinafter, each component will be described. The control unit C will be described later using functional blocks.
First, the power generation unit A is roughly divided into a power generation device 40, a rotary weight 45 that turns inside the device by capturing the movement of a user's arm and the like, converts kinetic energy into rotational energy, and generates power by rotating the rotary weight. And a speed-up gear 46 that converts the speed into a speed required for the transmission (speed increase) and transmits the speed to the power generation device 40 side.

The power generating device 40 is connected to the power generating stator 42 by the rotation of the rotary weight 45 being transmitted to the power generating rotor 43 via the speed increasing gear 46 and rotating the power generating rotor 43 inside the power generating stator 42. It functions as an electromagnetic induction type AC power generation device that outputs the electric power induced in the generated power generation coil 44 to the outside.
Therefore, the power generation unit A generates power using energy related to the life of the user, and can drive the timekeeping device 1 using the power.
Next, the power supply section B includes a rectifier circuit section 47, a large-capacity capacitor 48, and a step-up / step-down circuit 113.
The step-up / step-down circuit 113 is capable of multi-step boosting and stepping-down using a plurality of capacitors 113a, 113b and 113c, and adjusts a voltage supplied to the drive unit E by a control signal φ11 from the control unit C. be able to. The output voltage of the step-up / step-down circuit 113 is also supplied to the control unit C by the monitor signal φ12, so that the output voltage can be monitored. Here, the power supply section B takes Vdd (high potential side) as a reference potential (GND) and generates VTKN (low potential side) as a power supply voltage.

Next, the hand movement mechanism D will be described. The stepping motor 10 used in the hand driving mechanism D is also called a pulse motor, a stepping motor, a stepping motor, a digital motor, or the like, and is a motor driven by a pulse signal that is frequently used as an actuator of a digital control device. . In recent years, small and lightweight stepping motors have been widely used as actuators for small electronic devices or information devices suitable for carrying. A typical example of such an electronic device is a clock device such as an electronic timepiece, a time switch, or a chronograph.
The stepping motor 10 of the present embodiment includes a drive coil 11 that generates a magnetic force by a drive pulse supplied from a drive unit E, a stator 12 that is excited by the drive coil 11, and a magnetic field that is excited inside the stator 12. The rotor 13 is rotated by the rotation of the rotor 13. The stepping motor 10 is of a PM type (permanent magnet rotating type) in which the rotor 13 is formed of a disk-shaped two-pole permanent magnet. The stator 12 is provided with a magnetic saturation portion 17 so that different magnetic poles are generated in the respective phases (poles) 15 and 16 around the rotor 13 by the magnetic force generated by the drive coil 11. In order to define the rotation direction of the rotor 13, an inner notch 18 is provided at an appropriate position on the inner periphery of the stator 12, so that cogging torque is generated so that the rotor 13 stops at an appropriate position. ing.

The rotation of the rotor 13 of the stepping motor 10 is performed by the fifth wheel 51, the fourth wheel 52, the third wheel 53, the second wheel 54, the minute wheel 55, and the hour wheel 56 meshed with the rotor 13 through the pinion. Is transmitted to each needle by the train wheel 50. A second hand 61 is connected to the center of the fourth wheel & pinion 52, a minute hand 62 is connected to the second wheel & pinion 54, and an hour hand 63 is connected to the hour wheel & pinion 56. The time is displayed by each of these hands in conjunction with the rotation of the rotor 13. It is of course possible to connect a transmission system (not shown) for displaying the date and the like to the wheel train 50.
Next, the drive unit E supplies various drive pulses to the stepping motor 10 under the control of the control unit C. More specifically, by applying control pulses having different polarities and pulse widths at respective timings from the control unit C, drive pulses having different polarities are supplied to the drive coil 11, or the drive pulses for detecting the rotation of the rotor 13 are supplied. A detection pulse for exciting an induced voltage for detecting a magnetic field can be supplied.

[1.2] Functional Configuration of Control System Next, a functional configuration of the control system according to the first embodiment will be described with reference to FIG.
The timekeeping device 1 includes a power generation unit 101 that performs AC power generation, a power generation detection circuit 102 that detects power generation based on the generated voltage SK of the power generation unit 101, and outputs a power generation detection result signal SA, and an AC output from the power generation unit 101. A rectifier circuit 103 that rectifies a current and converts it into a DC current, a power storage device 104 that stores power by the DC current output from the rectifier circuit 103, and a device that operates with electric energy stored in the power storage device 104 to perform timekeeping control A timekeeping control circuit 105 that outputs a normal motor drive pulse SI and outputs a generator AC magnetic field detection timing signal SB for instructing a detection timing of the generator AC magnetic field detection; a power generation detection result signal SA and a power generation AC magnetic field detection A power generator that performs a generator AC magnetic field detection based on the timing signal SB and outputs a generator AC magnetic field detection result signal SC. And it is configured to include an AC magnetic field detecting circuit 106, a.

In addition, the timer 1 includes a duty-down counter 107 that outputs a normal motor drive pulse duty-down signal SH for controlling the duty-down of the normal motor drive pulse based on the generator AC magnetic field detection result signal SC; A correction drive pulse output circuit 108 that determines whether or not to output a correction drive pulse SJ based on the AC magnetic field detection result signal SC, and outputs a correction drive pulse SJ as necessary, and a normal motor drive pulse SI or correction drive A motor drive circuit 109 for outputting a motor drive pulse SL for driving the pulse motor 10 based on the pulse SJ; and a generator AC magnetic field detection result signal SC and an induced voltage signal SD output from the motor drive circuit 109. A high-frequency magnetic field that detects a high-frequency magnetic field and outputs a high-frequency magnetic field detection result signal SE A detection circuit 110, an AC magnetic field detection circuit 111 that detects an AC magnetic field based on the generator AC magnetic field detection result signal SC and the induced voltage signal SD output from the motor drive circuit 109, and outputs an AC magnetic field detection result signal SF; A rotation detection circuit 112 that detects whether the motor 10 has rotated based on the generator AC magnetic field detection result signal SC and the induced voltage signal SD output from the motor drive circuit 109, and outputs a rotation detection result signal SG; It is configured with.

[1.3] Power generation detection circuit [1.3.1] Configuration of power generation detection circuit FIG. 3 is an example of a circuit configuration around the power generation detection circuit when performing full-wave rectification.
In FIG. 3, a power generation detection circuit 102, a power generation unit 101 that performs AC power generation as peripheral circuits of the power generation detection circuit 102, and a rectification circuit 103 that rectifies an AC current output from the power generation unit 101 and converts the AC current into a DC current And a power storage device 104 that stores power by a DC current output from the rectifier circuit 103.
The power generation detection circuit 102 compares the voltage V1 of the first output terminal AG1 of the power generation unit 101 with the high-potential-side terminal voltage VDD of the power storage device 104, and outputs first comparison result data DC1; The second comparator COMP2, which compares the voltage V2 of the second output terminal AG2 of the power generation unit 101 with the high-potential terminal voltage VDD of the power storage device 104 and outputs second comparison result data DC2, and the first comparison result data DC1 And an OR circuit OR1 for calculating a logical sum of the second comparison result data DC2 and outputting the result as power generation detection data DDET.

Here, the comparators COMP1 and COMP2 will be described.
As described above, the present embodiment is for the case where full-wave rectification is performed, but the present invention is also applicable to the case of half-wave rectification.
That is, it is also possible to adopt a configuration as shown in FIG.
However, as shown in FIG. 16, when half-wave rectification is performed by the half-wave rectifier circuit 103 ′ and the power generation phase does not contribute to charging, the power generation by the generator 101 is several tens [V] at the maximum. Since the voltage is applied to the non-inverting input terminal (+) of the comparator COMP ', a device having a high withstand voltage is required as the comparator COMP'. In this case, the comparator COMP ′ operates by the power supply from the power storage device 104.

On the other hand, when full-wave rectification is performed as in the present embodiment, only a voltage of about +0.6 [V] of the voltage of the power storage device 104 is generated at the output terminals AG1 and AG2 of the generator 101 at the maximum. Therefore, it is possible to use devices with low withstand voltage as the comparators COMP1 and COMP2.
As a result, the comparators COMP1 and COMP2 can be manufactured by an IC process generally used for a timepiece, and the circuit size and cost can be reduced.
Therefore, when it is not necessary to use a device having a low withstand voltage and it is desired to simplify the circuit configuration, the configuration of the half-wave rectification shown in FIG. 16 can be adopted.

Next, an example of the comparators COMP1 and COMP2 connected to the high potential side voltage Vdd will be described with reference to FIG.
As shown in FIG. 13, each of the comparators COMP1 and COMP2 includes a pair of load transistors 211 and 212, a pair of input transistors 213 and 214, an output transistor 215, and constant current sources 216 and 217. Of these, the load transistors 211 and 212 and the output transistor 215 are of the P-channel field effect type, while the input transistors 213 and 214 are of the N-channel field effect type. The gates of the input transistors 213 and 214 are the negative input terminal (-) and the positive input terminal (+) of the comparator COMP1 (COMP2), respectively, while the drain of the output transistor 215 is the output terminal OUT.
In such a configuration, since the load transistors 211 and 212 form a current mirror circuit, current values flowing into the load transistors 211 and 212 are equal to each other. Therefore, the difference between the currents (voltages) flowing into the gates of the input transistors 213 and 214 is amplified, and the difference appears at the terminal A. Since the transistors 211 and 212 which receive the difference on the way receive only the same current value, The difference current (voltage) is gradually greatly amplified and flows into the gate of the transistor 215.

As a result, the drain voltage of the transistor 215, which is the output terminal OUT of the comparator 201, is slightly smaller than the gate current (voltage) of the transistor 214, which is the positive input terminal (+), of the transistor 214, which is the negative input terminal (-). However, if it exceeds, the voltage largely swings to the high-potential-side voltage Vdd, and if not, the voltage swings to the low-potential-side voltage Vss.
According to such a comparator COMP1 (COMP2), since the transistors 211 and 212 are used as active loads, it is not necessary to use one resistor other than the constant current sources 216 and 217. For this reason, it is extremely advantageous when integrated.
Generally, the response delay time of a comparator composed of MOS transistors is proportional to “Cg / Iop”, where Cg is the gate capacitance of the output transistor and Iop is the operating current of the comparator. That is, the response delay time and the current consumption are almost in inverse proportion. In an electronic timepiece driven by electric power from a built-in generator, the size of the generator is limited by the space of the electronic timepiece, and large power generation cannot be obtained. The current consumption of the circuit is reduced. Also in the comparators COMP1 and COMP2, it is necessary to reduce current consumption and minimize the operating current Iop, and the response delay time of the comparators COMP1 and COMP2 tends to be particularly large.

The rectifier circuit 103 includes a first rectifier element RE1 and a fourth rectifier element RE4 that are turned on when the voltage V1 of one output terminal AG1 of the power generation unit 101 becomes higher than the high-potential-side terminal voltage VDD of the power storage device 104; The second rectifier element RE2 and the third rectifier element RE3 are turned on when the voltage V2 of the other output terminal AG2 of the unit 101 becomes higher than the high-potential-side terminal voltage VDD of the power storage device 104.
In this case, the rectifiers RE1 to RE4 may be passive rectifiers such as diodes or active rectifiers combining a transistor and a comparator.
Next, the operation of the power generation detection circuit will be described.
When the power generation unit 101 starts power generation, the generated voltage is supplied to both output terminals AG1 and AG2. In this case, the phases of the terminal voltage V1 of the output terminal AG1 and the terminal voltage V2 of the output terminal AG2 are inverted.

When the terminal voltage V1 of the output terminal AG1 becomes higher than the voltage V2 of the output terminal AG2 by a predetermined voltage or more and the voltage of the output terminal AG1 becomes higher than the high-potential-side terminal voltage VDD of the power storage device 104, the first rectification occurs. The element RE1 and the fourth rectifying element RE4 are turned on. As a result, a generated current flows through the path of “terminal AG1 → first rectifying element RE1 → power supply VDD → power storage device 104 → power supply VTKN → fourth rectifying element RE4”, and electric charge is stored in power storage device 104.
Then, the first comparison result data DC1 output from the first comparator COMP1 becomes "H" level.
As a result, the power generation detection data DDET output from the OR circuit OR1 becomes "H" level, and power generation is detected.

Similarly, when terminal voltage V2 of output terminal AG2 becomes higher than high-potential-side terminal voltage VDD of power storage device 104, second rectifying element RE2 and third rectifying element RE3 are turned on. As a result, the generated current flows through the path of “terminal AG2 → second rectifier element RE2 → power supply VDD → power storage device 104 → power supply VTKN → third rectifier element RE3”, and the power storage device 104 is charged.
Then, the second comparison result data DC2 output from the second comparator COMP2 becomes "H" level.
As a result, the power generation detection data DDET output from the OR circuit OR1 becomes "H" level, and power generation is detected.
As described above, power generation having a voltage equal to or higher than the terminal voltage of the power storage device 104 can be detected, and power generation can be reliably detected.

[1.4]
Next, the operation of the timing device 1 will be described with reference to the processing flowchart of FIG.
First, it is determined whether or not one second has elapsed since the reset timing of the timer 1 or the previous drive pulse output (step S1).
If it is determined in step S1 that one second has not elapsed, it is not a timing to output a drive pulse, and thus a standby state is set.
If one second has elapsed in the determination of step S1, it is determined whether or not the state of charge of the power storage device has been detected by the power generation detection circuit 102 during the output of the high-frequency magnetic field detection pulse signal SP0 (step S2).

[1.4.1] Processing when power generation state in which power storage device 104 can be charged is detected by power generation detection circuit 102 during output of high frequency magnetic field detection pulse SP0 In the determination in step S2, high frequency magnetic field detection pulse signal If the power generation detection circuit 102 detects a power generation state in which the power storage device 104 can be charged during the output of SP0 (step S2; Yes), the duty ratio is reduced to reduce the effective power of the normal motor drive pulse K11. Reset (set to a predetermined initial duty down counter value) or stop counting down of the duty down counter (step S7).
In this case, counting by the duty down counter means that the motor is driven by the normal motor drive pulse K11 having a lower duty ratio at the next pulse motor drive timing. Due to the magnetic field, the pulse motor cannot be driven according to the normal motor drive pulse K11, and the correction drive pulse is likely to be output.
Therefore, the duty-down counter is reset or the count-down of the duty-down counter is stopped to prevent the duty ratio of the normal motor drive pulse K11 from being lowered at the next pulse motor drive timing.

Next, the output of the high-frequency magnetic field detection pulse SP0 is stopped (step S8).
Subsequently, a process of resetting the duty down counter for lowering the duty ratio so as to reduce the effective power of the normal motor drive pulse K11 (setting to a predetermined initial duty down counter value) or stopping the countdown of the duty down counter is performed. (Step S9), this process is provided for the case where the determination in step S3 described later is Yes. Since the process has already been performed in step S7, No processing is performed.
Next, the output of the AC magnetic field detection pulse SP11 and the AC magnetic field detection pulse SP12 is stopped (step S10).
Subsequently, a process of resetting the duty down counter for lowering the duty ratio so as to reduce the effective power of the normal motor drive pulse K11 (setting to a predetermined initial duty down counter value) or stopping the countdown of the duty down counter is performed. (Step S11), this process is provided for the case where the determination in step S4 described later is Yes. Since the process has already been performed in step S7, No processing is performed.

Next, the output of the normal drive motor pulse K11 is stopped (or interrupted) (step S12).
Subsequently, a process of resetting the duty down counter for lowering the duty ratio so as to reduce the effective power of the normal motor drive pulse K11 (setting to a predetermined initial duty down counter value) or stopping the countdown of the duty down counter is performed. (Step S13), this process is provided for the case where the determination in Step S5 described later is Yes. Since the process has already been performed in Step S7, No processing is performed.
Next, the output of the rotation detection pulse SP2 is stopped (step S14).
Then, the correction driving pulse P2 + Pr is output (step S15). In this case, it is the correction drive pulse P2 that actually drives the pulse motor 10, and the correction drive pulse Pr is for suppressing the post-rotation vibration of the driven rotor and quickly shifting to a stable state. It is.
Next, in order to cancel the residual magnetic flux accompanying the application of the correction drive pulse P2 + Pr, a demagnetization pulse PE having a polarity opposite to the polarity of the correction drive pulse P2 + Pr is output (step S16).

Here, the role of the degaussing pulse PE will be described.
Originally, an induced voltage should be generated in the motor drive coil due to the leakage magnetic flux of the generator.
However, when the AC drive voltage P2 + Pr is applied when the AC magnetic field detection voltage based on the AC magnetic field detection pulse exceeds the threshold, the correction drive pulse P2 + Pr has a large effective power and is induced in the motor drive coil by the residual magnetic flux. No voltage is generated.
In the normal state, the voltage detected by the rotation detection pulse SP2 when the pulse motor is not rotating does not exceed the threshold value. However, the leakage of the generator is affected by the residual magnetic flux after the application of the correction drive pulse P2 + Pr. There is a case where the magnetic flux is superimposed on the detection voltage and exceeds the threshold value, thereby being erroneously set as the detection voltage at the time of rotation.
Therefore, in order to eliminate these effects, the residual magnetic flux is erased by applying a degaussing pulse PE having a polarity opposite to that of the correction driving pulse P2 + Pr.
In this case, it is more effective to output the demagnetizing pulse PE immediately before the external magnetic field detection timing.

Further, the pulse width of the degaussing pulse PE is a narrow (short) pulse that does not rotate the rotor, and it is desirable to use a plurality of intermittent pulses in order to further enhance the degaussing effect.
After the output of the degaussing pulse PE is completed, the count of the duty down counter is restarted (step S17), and the duty ratio of the normal drive pulse K11 is set so as to minimize power consumption and not output the correction drive pulse P2 + Pr.
Then, the process returns to step S1 to repeat the same process.

[1.4.2] Processing when power generation detecting circuit 102 detects a power generation state in which power storage device 104 can be charged during output of AC magnetic field detection pulse SP11 or AC magnetic field detection pulse SP12 In the determination of step S2 If no power generation state in which the power storage device 104 can be charged by the power generation detection circuit 102 is detected during the output of the high-frequency magnetic field detection pulse signal SP0 (Step S2; No), the AC magnetic field detection pulse SP11 or AC It is determined whether or not the state of charge of the power storage device is detected by the power generation detection circuit 102 during the output of the magnetic field detection pulse SP12 (step S3).
In the determination in step S3, when the power generation detection circuit 102 detects a power generation state in which the power storage device 104 can be charged during the output of the AC magnetic field detection pulse SP11 or the AC magnetic field detection pulse SP12 (step S3; Yes). The duty-down counter for reducing the duty ratio to reduce the effective power of the normal motor drive pulse K11 is reset (set to a predetermined initial duty-down counter value) or the count-down of the duty-down counter is stopped (step S9). ).

Next, the output of the AC magnetic field detection pulse SP11 and the AC magnetic field detection pulse SP12 is stopped (step S10).
Subsequently, a process of resetting the duty down counter for lowering the duty ratio so as to reduce the effective power of the normal motor drive pulse K11 (setting to a predetermined initial duty down counter value) or stopping the countdown of the duty down counter is performed. (Step S11), but this process is provided for the case where the determination in step S4 described later is Yes. Since the process has already been performed in step S9, No processing is performed.
Next, the output of the normal drive motor pulse K11 is stopped (or interrupted) (step S12).

Subsequently, a process of resetting the duty down counter for lowering the duty ratio so as to reduce the effective power of the normal motor drive pulse K11 (setting to a predetermined initial duty down counter value) or stopping the countdown of the duty down counter is performed. (Step S13), but this processing is provided for the case where the determination in Step S5 described later is Yes. Since the processing has already been performed in Step S9, No processing is performed.
Next, the output of the rotation detection pulse SP2 is stopped (step S14).
Then, the correction driving pulse P2 + Pr is output (step S15). In this case, it is the correction drive pulse P2 that actually drives the pulse motor 10, and the correction drive pulse Pr is for suppressing the post-rotation vibration of the driven rotor and quickly shifting to a stable state. It is.
Next, in order to cancel the residual magnetic flux accompanying the application of the correction drive pulse P2 + Pr, a demagnetization pulse PE having a polarity opposite to the polarity of the correction drive pulse P2 + Pr is output (step S16).

After the output of the degaussing pulse PE is completed, the count of the duty down counter is restarted (step S17), and the duty ratio of the normal drive pulse K11 is set so as to minimize power consumption and not output the correction drive pulse P2 + Pr.
Then, the process returns to step S1 to repeat the same process.

[1.4.3] Processing when power generation detecting circuit 102 detects a power generation state in which power storage device 104 can be charged during output of normal drive pulse K11 In the determination of step S3, AC magnetic field detection pulse SP11 or AC When the power generation detection circuit 102 does not detect the power generation state in which the power storage device 104 can be charged during the output of the magnetic field detection pulse SP12 (step S3; No), the power generation detection circuit 102 does not output the normal drive pulse K11. It is determined whether or not the state of charge of the power storage device is detected (step S4).
If it is determined in step S4 that the power generation detection circuit 102 detects a power generation state in which the power storage device 104 can be charged during the output of the normal drive pulse K11 (step S4; Yes), the effective power of the normal motor drive pulse K11 is determined. Is reset (set to a predetermined initial duty down counter value) or the count down of the duty down counter is stopped (step S11).

Next, the output of the normal drive pulse K11 is stopped (or interrupted) (step S12).
Subsequently, a process of resetting the duty down counter for lowering the duty ratio so as to reduce the effective power of the normal motor drive pulse K11 (setting to a predetermined initial duty down counter value) or stopping the countdown of the duty down counter is performed. (Step S13), this processing is provided for the case where the determination in step S5 described later is Yes. Since the processing has already been performed in step S11, No processing is performed.
Next, the output of the rotation detection pulse SP2 is stopped (step S14).
Then, the correction driving pulse P2 + Pr is output (step S15).

Next, in order to cancel the residual magnetic flux accompanying the application of the correction drive pulse P2 + Pr, a demagnetization pulse PE having a polarity opposite to the polarity of the correction drive pulse P2 + Pr is output (step S16).
After the output of the degaussing pulse PE is completed, the count of the duty down counter is restarted (step S17), and the duty ratio of the normal drive pulse K11 is set so as to minimize power consumption and not output the correction drive pulse P2 + Pr.
Then, the process returns to step S1 to repeat the same process.

[1.4.4] Processing when power generation state in which power storage device 104 can be charged is detected by power generation detection circuit 102 during output of rotation detection pulse SP2 In the determination of step S4, during normal drive pulse K11 is output. If a power generation state in which the power storage device 104 can be charged is not detected by the power generation detection circuit 102 (Step S4; No), power generation in which the power storage device 104 can be charged by the power generation detection circuit 102 during the output of the rotation detection pulse SP2. It is determined whether a state has been detected (step S5).
In the determination of step S5, when the power generation detecting circuit 102 detects a power generation state in which the power storage device 104 can be charged during the output of the rotation detection pulse SP2 (step S5; Yes), the effective power of the normal motor drive pulse K11 Is reset (set to a predetermined initial duty down counter value) or the count down of the duty down counter is stopped (step S13).

Next, the output of the rotation detection pulse SP2 is stopped (or interrupted) (step S14).
Then, the correction driving pulse P2 + Pr is output (step S15).
Next, in order to cancel the residual magnetic flux accompanying the application of the correction drive pulse P2 + Pr, a demagnetization pulse PE having a polarity opposite to the polarity of the correction drive pulse P2 + Pr is output (step S16).
After the output of the degaussing pulse PE is completed, the count of the duty down counter is restarted (step S17), and the duty ratio of the normal drive pulse K11 is set so as to minimize power consumption and not output the correction drive pulse P2 + Pr.
Then, the process returns to step S1 to repeat the same process.

[1.4.5] Processing when power generation state in which power storage device 104 can be charged is not detected While the pulse signal SP0 for high-frequency magnetic field detection is being output, the charging state is not detected (step S2; No), and the AC magnetic field is not detected. No power generation state capable of charging power storage device 104 is detected during output of detection pulse SP11 or AC magnetic field detection pulse SP12 (step S3; No), and power storage device 104 is charged during output of normal drive pulse K11. If a possible power generation state is not detected (Step S4; No) and a charging state is not detected even during the output of the rotation detection pulse SP2 (Step S5; No), the duty of the next normal drive pulse K11 is changed. When the condition that can be reduced is satisfied, the duty can be reduced from the duty of the current normal drive pulse K11, or the duty can be further reduced. If not, that is, if it is the preset minimum duty, pulse width control is performed to maintain the duty ratio as it is (step S6).

[1.5] Effects of First Embodiment As described above, according to the first embodiment, a power generation state capable of reliably charging a power storage device is detected, and a countermeasure for preventing an adverse effect in the power generation state is provided. Can be ensured, and unnecessary measures need not be taken, so that power consumption can be reduced.
Further, the configuration of the first embodiment is a configuration for detecting the generated voltage, and can detect the generated current without affecting the charging performance, such as inserting a resistor in the charging path. Unlike the power generation detection method having the configuration described above, the power generation detection operation does not cause a decrease in the charging performance, so that the detection can be always performed.

[2] Second Embodiment In the first embodiment, the power generation detection circuit 102 directly compares the generated voltage of the power generation unit 101 with the high potential side terminal voltage of the power storage device 104. This embodiment is an embodiment in which the charged state is detected more reliably by using the high potential side terminal voltage of the power storage device 104 + a predetermined offset voltage instead of the high potential side terminal voltage of the power storage device 104.

[2.1] Power generation detection circuit [2.1.1] Configuration of power generation detection circuit Fig. 5 shows an example of a circuit configuration around the power generation detection circuit. 5, the same parts as those in FIG. 3 are denoted by the same reference numerals.
In FIG. 5, a power generation detection circuit 102A, a power generation unit 101 that performs AC power generation, and a rectification circuit 103 that rectifies an AC current output from the power generation unit 101 and converts the AC current into a DC current as peripheral circuits of the power generation detection circuit 102A. And a power storage device 104 that stores power by a DC current output from the rectifier circuit 103.
The power generation detection circuit 102 includes a first offset voltage adding circuit OS1 that adds a predetermined offset voltage to the high potential terminal voltage VDD of the power storage device 104 and outputs a first offset terminal voltage VOS1, and a high potential side voltage of the power storage device 104. A second offset voltage adding circuit OS2 for adding a predetermined offset voltage to the terminal voltage VDD to output a second offset terminal voltage VOS2, a voltage V1 of the first output terminal AG1 of the power generation unit 101, and a first offset terminal voltage VOS1; The first comparator COMP1 that outputs the first comparison result data DC11, the voltage V2 of the second output terminal AG2 of the power generation unit 101 and the second offset terminal voltage VOS2 are compared, and the second comparison result data The second comparator COMP2 that outputs DC12 and the logical sum of the first comparison result data DC1 and the second comparison result data DC2 are obtained and output as power generation detection data DDET1. And it is configured to include an OR circuit OR1, a to.

Here, the comparators COMP1 and COMP2 will be described.
The comparators COMP1 and COMP2 are configured to input the voltage level-shifted by the offset voltage adding circuits OS1 and OS2. In such a configuration, the threshold voltages Vth of the input transistors 213 and 214 in FIG. It is also possible to make them different.
More specifically, if the threshold voltage Vth of the transistor 213 on the negative input terminal (-) side is made higher than that of the transistor 214 on the positive input terminal (+) side, the offset voltage adding circuits OS1, OS2 in FIG. The same operation and effect as those described above can be realized.
In this case, the threshold voltages Vth of the input transistors 213 and 214 can be made different by changing the transistor size. Specifically, the threshold voltage Vth of the input transistor 213 can be increased by making the gate width of the input transistor 213 smaller than the gate width of the input transistor 214. Further, the threshold voltages Vth of the input transistors 213 and 214 can be made different by a process method such as implantation of impurities.

As shown in FIG. 14, by connecting transistors having the same size and the same capacity in parallel, a circuit equivalent to the transistor 213 or the transistor 214 can be realized. That is, instead of the transistor 213, two transistors 213A and 213B having the same size and the same capacity are connected in parallel, and instead of the transistor 214, transistors 214A, 214B and 214C having the same size and the same capacity are connected in parallel.
With such a configuration, the capacity of the differential pair transistor is higher on the positive input terminal (+) side, and the terminal voltage on the negative input terminal (−) side is higher than the voltage on the positive input terminal (+) side. Otherwise, the transistors 214A, 214B, 214C will not be turned on, and the comparator output will not be inverted.

As a detection operation in the comparator, for example, when the high potential side voltage Vdd is applied to the positive input terminal (+) side with respect to the positive input terminal (+) side, the negative input terminal (−) side is higher than the voltage Vdd. Only when a voltage higher than the voltage Vdd + α by the voltage α is applied, the comparator inverts and outputs the “L” level.
Next, the operation of the power generation detection circuit will be described.
When the power generation unit 101 starts power generation, the generated voltage is supplied to both output terminals AG1 and AG2. In this case, the phases of the terminal voltage V1 of the output terminal AG1 and the terminal voltage V2 of the output terminal AG2 are inverted. Further, the offset voltages VOS1 and VOS2 are set based on the forward voltage VF of the rectifier elements RE1 and RE2. That is, when rectification is performed by a diode having a relatively large forward voltage VF, the offset voltage is set to about several hundred [mV]. When active rectification is performed by a transistor having a relatively small forward voltage VF, the offset voltage is set. Is set to about several tens [mV].

Then, the terminal voltage V1 of the output terminal AG1 becomes higher than the voltage V2 of the output terminal AG2 by a predetermined voltage or more, and the voltage of the output terminal AG1 becomes equal to the first offset voltage VOS1 (= the high-potential-side terminal voltage VDD of the power storage device 104 + offset). Voltage), the first rectifying element RE1 and the fourth rectifying element RE4 become conductive.
At this time, since the voltage of the output terminal AG1 is higher than the high-potential-side terminal voltage VDD of the power storage device 104, “the terminal AG1 → the first rectifying element RE1 → the power supply VDD → the power storage device 104 → the power supply VTKN → the fourth rectification” The generated current flows through the path of the element RE4, and the electric storage device 104 is charged.
Then, the first comparison result data DC11 output from the first comparator COMP1 becomes "H" level.
As a result, the power generation detection data DDET1 output from the OR circuit OR1 becomes "H" level, and charging is detected.

Similarly, when terminal voltage V2 of output terminal AG2 becomes higher than high-potential-side terminal voltage VDD of power storage device 104, second rectifying element RE2 and third rectifying element RE3 are turned on.
At this time, if the voltage of the output terminal AG2 becomes higher than the high-potential-side terminal voltage VDD of the power storage device 104 and becomes higher than the second offset voltage VOS2 (= the high-potential-side terminal voltage VDD of the power storage device 104 + offset voltage), The generated current flows through the path of “terminal AG2 → second rectifier element RE2 → power supply VDD → power storage device 104 → power supply VTKN → third rectifier element RE3”, and the power storage device 104 is charged with electric charge.
Then, the second comparison result data DC2 output from the second comparator COMP2 becomes "H" level.
As a result, the power generation detection data DDET1 output from the OR circuit OR1 becomes "H" level, and charging is detected.
As a method of providing an offset voltage for obtaining the same effect as described above, a voltage corresponding to the offset voltage is subtracted from the voltage at the output terminal side of the power generation unit 101, and then input to the comparator. The input voltage may be compared with the voltage of the power supply VDD, or one of the two input voltages may be offset in the comparator by an amount corresponding to the offset voltage. It is also possible to configure so that the level is offset by an amount corresponding to the offset voltage.

[2.2] Effect of Second Embodiment As described above, according to the second embodiment, a case where a generated current of a certain level or more flows is detected, so that a power generation state is detected more reliably. It is possible to reliably take measures for preventing adverse effects in the state of charge, and to eliminate unnecessary measures, thereby reducing power consumption.
Further, the configuration of the second embodiment is a configuration for detecting the generated voltage, and can detect the generated current without affecting the charging performance, such as inserting a resistor in the charging path. Unlike the power generation detection method having the configuration described above, the power generation detection operation does not cause a decrease in the charging performance, so that the detection can be always performed.

[3] Third Embodiment Next, a more specific third embodiment of the power generation detection circuit will be described with reference to FIGS.
[3.1] Configuration around power generation detection circuit FIG. 6 shows a circuit configuration example around the power generation detection circuit according to the third embodiment.
In FIG. 6, a power generation detection circuit 102B, a power generation unit 101 that performs AC power generation, and a rectification circuit 103B that rectifies an AC current output from the power generation unit 101 and converts the AC current into a DC current as peripheral circuits of the power generation detection circuit 102B. And a power storage device 104 that stores power by a DC current output from the rectifier circuit 103B.
The power generation detection circuit 102B calculates the NAND of the outputs of the first and second comparators COMP11 and COMP12, which will be described later, and outputs the result as the original power generation detection data DDET10. And a smoothing circuit 202 for smoothing using a C integration circuit and outputting the data as power generation detection data DDET11.

As shown in FIG. 7, the smoothing circuit 202 includes a resistor R1 and a capacitor C1 connected between the output terminal of the resistor R1 and the low-potential power supply VTKN.
The rectifier circuit 103B includes a first comparator COMP11 for performing on / off control of the first transistor Q1 to perform active rectification by comparing the voltage of one output terminal AG1 of the power generation unit 101 with the reference voltage Vdd; A second comparator COMP12 for performing active rectification by alternately turning on / off the second transistor Q2 with the first transistor by comparing the voltage of the other output terminal AG2 of the power generation unit 101 with the reference voltage Vdd; A third transistor Q3 that is turned on when a terminal voltage V2 of a terminal AG2 of the power generation unit 101 exceeds a predetermined threshold voltage, and is turned on when a terminal voltage V1 of a terminal AG1 of the power generation unit 101 exceeds a predetermined threshold voltage. And a fourth transistor Q4.
The diode d connected in parallel with the first to fourth transistors Q1 to Q4 used for rectification is used when there is not enough power supply voltage to control the on / off of the rectification transistors Q1 to Q4. A schottky diode may be externally connected, or if a parasitic diode is used, all circuits can be integrated.

[3.2] Operation During Charging First, the charging operation will be described.
When the power generation unit 101 starts power generation, the generated voltage is supplied to both output terminals AG1 and AG2. In this case, the phases of the terminal voltage V1 of the output terminal AG1 and the terminal voltage V2 of the output terminal AG2 are inverted.
When the terminal voltage V1 of the output terminal AG1 exceeds the threshold voltage, the fourth transistor Q4 turns on. Thereafter, when the terminal voltage V1 rises and exceeds the voltage of the power supply VDD, the output of the first comparator COMP11 becomes "L" level, and the first transistor Q1 is turned on.
On the other hand, since the terminal voltage V2 of the output terminal AG2 is lower than the threshold voltage, the third transistor Q3 is off, the terminal voltage V2 is lower than the voltage of the power supply VDD, and the output of the second comparator COMP12 is "H". Level, and the second transistor Q2 is off.

Therefore, during the period in which the first transistor Q1 is in the ON state, a generated current flows through the path of “terminal AG1 → first transistor → power supply VDD → power storage device 104 → power supply VTKN → fourth transistor Q4”, and charge is stored in the power storage device 104. Is charged.
Thereafter, when the terminal voltage V1 falls, the terminal voltage V1 of the output terminal AG1 becomes lower than the voltage of the power supply VDD, the output of the first comparator COMP11 becomes "H" level, the first transistor Q1 is turned off, and the output The terminal voltage V1 of the terminal AG1 falls below the threshold voltage of the fourth transistor Q4, and the transistor Q4 is also turned off.
On the other hand, when the terminal voltage V2 of the output terminal AG2 exceeds the threshold voltage, the third transistor Q3 turns on. Thereafter, when the terminal voltage V2 further rises and exceeds the voltage of the power supply VDD, the output of the second comparator COMP2 becomes "L" level, and the second transistor Q2 is turned on.
Therefore, during the period when the second transistor Q2 is in the ON state, the generated current flows through the path of “terminal AG2 → second transistor Q2 → power supply VDD → power storage device 104 → power supply VTKN → third transistor Q3”. The charge will be charged.

As described above, when the generated current flows, either the output of the first comparator COMP11 or the output of the second comparator COMP12 is at the “L” level.
Therefore, the NAND circuit 201 of the power generation detection circuit 102A performs a negation of the logical product of the outputs of the first comparator COMP1 and the second comparator COMP12, so that the original power generation detection data of “H” level in a state where the generated current is flowing. DDET10 is output to the smoothing circuit 202.
In this case, since the output of the NAND circuit 201 includes switching noise, the smoothing circuit 202 smoothes the output of the NAND circuit 201 using the RC integration circuit and outputs the smoothed output as the power generation detection data DDET11. .

[3.3] Specific operation example of power generation detection circuit Next, the operation of the power generation detection circuit of the third embodiment will be described with reference to the timing chart of FIG.
The power generation unit 101 starts power generation from time t0, and at time t1, when the voltage of the output terminal AG2 exceeds the voltage of the high-potential-side power supply VDD, the output of the second comparator COMP12 becomes "L", and the second transistor Q2 It turns on.
As a result, as described above, the generated current flows through the path of “terminal AG2 → second transistor Q2 → power supply VDD → power storage device 104 → power supply VTKN → third transistor Q3”, and electric charge is stored in power storage device 104. It becomes.
On the other hand, at time t1, since the voltage of the output terminal AG1 is lower than the voltage of the low potential side power supply VTKN, the output of the first comparator COMP11 remains "H".
As a result, one input terminal of the NAND circuit 201 becomes "L", the other input terminal becomes "H", and the original power generation detection data DDET10 becomes "H" level.
The "H" level original power generation detection data DDET10 input to the smoothing circuit 202 is smoothed, and at time t2, the power generation detection data DDET11 is set to "H" level to notify that it is in a charged state. .

Thereafter, at time t3, the voltage of the output terminal AG2 becomes lower than the voltage of the high-potential-side power supply VDD, the output of the second comparator COMP12 goes to the "H" level again, and both input terminals of the NAND circuit 201 go to the "H" level. It becomes.
As a result, the original power generation detection data DDET10 becomes the “L” level, but the operation of the smoothing circuit 202 keeps the power generation detection data DDET11 at the “H” level.
At time t4, when the voltage of the output terminal AG1 exceeds the voltage of the high-potential power supply VDD, the output of the first comparator COMP11 becomes "L" and the first transistor Q1 is turned on.
As a result, as described above, the generated current flows through the path of “terminal AG1 → first transistor Q1 → power supply VDD → power storage device 104 → power supply VTKN → fourth transistor Q4”, and the power storage device 104 is charged. It becomes.
On the other hand, at time t4, since the voltage of the output terminal AG2 is lower than the voltage of the low-potential-side power supply VTKN, the output of the second comparator COMP12 remains "H".
As a result, one input terminal of the NAND circuit 201 becomes "L", the other input terminal becomes "H", and the original power generation detection data DDET10 becomes "H" level.
The "H" level original power generation detection data DDET10 input to the smoothing circuit 202 is smoothed, and the power generation detection data DDET11 is held at "H" level.

Thereafter, at time t5, the voltage of the output terminal AG1 becomes lower than the voltage of the high-potential-side power supply VDD, the output of the first comparator COMP11 goes to the "H" level again, and both input terminals of the NAND circuit 201 go to the "H" level. It becomes.
As a result, the original power generation detection data DDET10 becomes the “L” level, but the operation of the smoothing circuit 202 keeps the power generation detection data DDET11 at the “H” level.
Next, from time t6 to time t9, the same operation as the operation from time t1 to time t5 is performed.
In this case, the power generation detection data DDET11 is maintained at the “H” level as usual due to the operation of the smoothing circuit 202.
However, after that, the power generation unit 101 interrupts the power generation, and at time t10, the power generation detection data DDET11 becomes the “L” level, and a notification that the charging has been interrupted is given.

[3.4] Effects of Third Embodiment As described above, according to the third embodiment, it is possible to reliably detect the state of charge even when active rectification is performed on a generated AC current. Become.
Further, the comparator used for active rectification can be shared with the power generation detection circuit, and the efficiency of the circuit can be improved.

[4] Fourth Embodiment A fourth embodiment is a specific embodiment in which the power generation detection circuit of the present invention is applied to a double boost rectifier circuit.
[4.1] Configuration around power generation detection circuit FIG. 9 shows an example of a circuit configuration around the power generation detection circuit according to the fourth embodiment.
In FIG. 9, a power generation detection circuit 102C, a power generation unit 101 that performs AC power generation, a boosting capacitor CUP that stores the AC current output from the power generation unit 101, and a boosting capacitor as peripheral circuits of the power generation detection circuit 102C. In order to turn on the transistor Q10 when the voltage at the output terminal AG of the boosting capacitor CUP exceeds the voltage of the high-potential-side power supply VDD of the power storage device 104, the first transistor Q10 which is turned on when charging the CUP, and " The comparator COMP13 that outputs an output signal at L level, the rectifier transistor Q11 that is turned on when the power storage device 104 is charged, and the voltage of the output terminal AG of the boosting capacitor CUP are set to the low potential side power supply VTKN of the power storage device 104. The comparator CO which outputs the "H" level original power generation detection signal DDET20 to turn on the rectifying transistor Q11 when the voltage becomes lower than MP14.
The power generation detection circuit 102C has the same configuration as the smoothing circuit 202 in the third embodiment, except for the time constant.

Here, the configuration of the comparator COMP14 will be described with reference to FIG.
As shown in FIG. 15, the comparator COMP14 includes a pair of load transistors 231 and 232, a pair of input transistors 233 and 234, an output transistor 235, and constant current sources 236 and 237. Of these, the load transistors 231 and 232 and the output transistor 235 are of the N-channel field effect type, while the input transistors 233 and 234 are of the P-channel field effect type. The gates of the input transistors 233 and 234 serve as the negative input terminal (-) and the positive input terminal (+) of the comparator COM3 (COM4), respectively, while the drain of the output transistor 235 serves as the output terminal OUT.
As described above, the comparator COMP14 has a polarity completely opposite to that of the comparator COMP1 (COMP2) (see FIG. 13) connected to the high potential side voltage Vdd. Also in this comparator COMP14, similarly to the comparator COMP1 (COMP2), the threshold voltage Vth of the input transistors 233 and 234 is made different, whereby the offset voltage adding circuit can be taken in the inside.

More specifically, if the threshold voltage Vth of the transistor 233 on the negative input terminal (−) side is made larger in absolute value than that of the transistor 234 on the positive input terminal (+) side, the offset voltage adding circuit in FIG. The same operational effects as those of OS1 and OS2 can be realized. The method of making the threshold voltages Vth of the input transistors 233 and 234 different is the same as that of the comparator COMP1 (COMP2) shown in FIG.
Also in the case of this embodiment, as in the case of FIG. 3, when performing full-wave rectification, the output terminals AG1 and AG2 of the generator 101 are connected to the voltage of the power storage device 104 at most +0.6 [V]. ], A low-voltage device can be used as the comparator COMP14. Therefore, the comparator COMP14 can be manufactured by an IC process generally used for a timepiece, and the circuit size and cost can be reduced.

[4.2] Operation during Charging First, the charging operation will be described with reference to the operation timing chart of FIG.
The charging operation of the compensation rectifier circuit is roughly divided into a charging operation of the boosting capacitor CUP and a charging operation of the power storage device 104, which will be sequentially described below.
In the initial state, the voltage of the output terminal AG of the boosting capacitor CUP is lower than the voltage of the high-potential power supply VDD of the power storage device 104 and is equal to or higher than the voltage of the low-potential power supply VTKN of the power storage device 104. .
At time t0, the power generation unit 101 starts power generation. In the initial state, the voltage of the output terminal AG of the boosting capacitor CUP is lower than the voltage of the high-potential power supply VDD of the power storage device 104, and , The comparator COMP13 outputs an "H" level output signal, and the comparator COMP14 outputs "L" level original power generation detection data DDET20.

Therefore, at this time, the transistor Q10 is off and the rectifying transistor Q11 is off.
At time t1, when the voltage of the output terminal AG exceeds the voltage of the high-potential power supply VDD of the power storage device 104, the comparator COMP13 outputs an "L" level output signal, and the transistor Q10 is turned on.
As a result, the boosting capacitor CUP is charged.
Then, at time t2, when the voltage of the output terminal AG becomes lower than the voltage of the high-potential power supply VDD of the power storage device 104 again, the comparator COMP13 outputs an "H" level output signal, and the transistor Q10 is turned off. The charging operation of the boosting capacitor CUP is interrupted.
At time t3, when the voltage of the output terminal AG becomes lower than the voltage of the low-potential-side power supply VTKN of the power storage device 104, the comparator COMP14 outputs the original power generation detection data DDET20 at "H" level.
As a result, the rectifying transistor Q11 is turned on, and a power generation current flows through the path of the power generation unit 101 → the power storage device 104 → the rectification transistor Q11 → the boosting capacitor CUP → the power generation unit 101. Charging is performed at twice the voltage.

On the other hand, at time t4, the power generation detection data DDET21 is set to the "H" level because the comparator COMP14 outputs the "H" level output signal.
Thereafter, at time t5, when the voltage of the output terminal AG exceeds the voltage of the low-potential-side power supply VTKN of the power storage device 104, the original power generation detection data DDET20 of the comparator COMP14 becomes "L" level.
However, the power generation detection data DDET21 is still maintained at the “H” level due to the smoothing action of the power generation detection circuit 102C.
The original power generation detection data DDET20 is output.
Next, from time t6 to time t9, the same operation as the operation from time t1 to time t5 is performed.
In this case, the power generation detection data DDET21 is maintained at the “H” level as usual due to the smoothing action of the power generation detection circuit 102C.
At time t10, when the voltage of the output terminal AG again exceeds the voltage of the high-potential power supply VDD of the power storage device 104, the comparator COMP13 outputs an "L" level output signal, the transistor Q10 turns on, and the boosting capacitor CUP Will be stored.

Then, at time t11, when the voltage of the output terminal AG becomes lower than the voltage of the high-potential power supply VDD of the power storage device 104 again, the comparator COMP13 outputs an output signal of "H" level, and the transistor Q10 is turned off. The charging operation of the boosting capacitor CUP is interrupted.
At time t12, when the voltage of the output terminal AG becomes lower than the voltage of the low-potential-side power supply VTKN of the power storage device 104, the comparator COMP14 outputs the original power generation detection data DDET20 at "H" level.
As a result, the rectifying transistor Q11 is turned on, and a power generation current flows through the path of the power generation unit 101 → the power storage device 104 → the rectification transistor Q11 → the boosting capacitor CUP → the power generation unit 101. Charging is performed at twice the voltage.
Thereafter, at time t13, when the voltage of the output terminal AG exceeds the voltage of the low-potential power supply VTKN of the power storage device 104, the original power generation detection data DDET20 of the comparator COMP14 becomes "L" level.
However, thereafter, the power generation unit 101 interrupts the power generation, and at time t14, the power generation detection data DDET11 becomes the “L” level, and a notification that the charging has been interrupted is given.

[4.3] Effect of Fourth Embodiment As described above, according to the fourth embodiment, even when the generated alternating current is boosted and rectified twice, the charged state can be reliably detected. It becomes possible.

[5] Fifth Embodiment The fifth embodiment is different from the above embodiments in that power generation is detected by detecting a limiter current accompanying power generation at the time of a limiter circuit operation instead of a generated current accompanying power generation. It is.
FIG. 11 is a diagram illustrating a configuration of a charging circuit including a power generation detection circuit and a limiter circuit according to a fifth embodiment.
In FIG. 11, the charging circuit detects the charging voltage Va of the large-capacity capacitor 104, compares the charging voltage Va with a reference voltage, and when the charging voltage Va becomes equal to or higher than the reference voltage, a limiter signal SLIM for preventing overcharging. A detection circuit 151 that outputs a control signal CS1 that delays the rising timing of the limiter signal SLIM based on the limiter signal SLIM; and a control circuit 152 that outputs a control signal CS2 that delays the falling timing of the limiter signal SLIM. The comparator CMP1A compares the voltage of the power supply VDD with the terminal voltage V1 of the output terminal AG1 of the power generation unit 101 and outputs a comparison result signal d. The comparator CMP1A outputs the voltage of the high potential power supply VDD and the terminal voltage V2 of the output terminal AG2 of the power generation unit 101. A comparator CMP1B for comparing and outputting a comparison result signal f, a voltage of the low potential side power supply VTKN and And a comparator CMP2A for comparing the terminal voltage V1 of the output terminal AG1 of the power supply unit AG1 and outputting a comparison result signal h, and comparing the voltage of the low potential side power supply VTKN with the terminal voltage V2 of the output terminal AG2 of the power generation unit 101 to output a comparison result signal j. A comparator CMP2B, a logical AND of the control signal CS1 supplied to the inverting input terminal and a comparison result signal d supplied to the other input terminal, and outputs a drive signal e; AND circuit 154 which outputs the drive signal g by taking the logical product of the control signal CS1 and the comparison result signal f supplied to the other input terminal, and the control signal CS2 supplied to the inverted input terminal and the other input terminal And an AND circuit 155 that outputs the drive signal i by taking the logical product of the comparison result signal h supplied to the inverter 155 and the control signal CS supplied to the inverting input terminal. 2 and an AND circuit 156 that outputs a drive signal k by taking the logical product of the comparison result signal j supplied to the other input terminal, a source connected to the high potential side power supply VDD, and a drain connected to the output terminal AG1. A P-channel FET MP1 whose on / off control is performed by the drive signal e, a P-channel FET MP2 whose source is connected to the high potential side power supply VDD, whose drain is connected to the output terminal AG2, and whose on / off control is performed by the drive signal g. , The source is connected to the low-potential power supply VSS, the drain is connected to the output terminal AG1, the N-channel FET MN1 whose on / off is controlled by the drive signal i, the source is connected to the low-potential power supply VSS, and the drain is An N-channel FET MN2 connected to the terminal AG2 and on / off controlled by a drive signal k; a comparison result signal d and a comparison result signal Equipped with a power generation detecting circuit 158 for generating power detected based on f are configured.

Next, the operation at the time of power generation detection will be described.
The control signal CS1 whose rising timing is delayed with respect to the limiter signal SLIM is supplied to the inverting input terminals of the AND circuits 153 and 154, and the control signal CS2 whose falling timing is delayed is supplied to the AND circuits 155 and AND. By supplying the signal to the inverting input terminal of the circuit 156, the off time of the N-channel FETs MN1 and MN2 is controlled to be longer than the on-time of the P-channel FETs MP1 and MP2.
More specifically, when the limiter signal SLIM becomes “H” level, first, the N-channel FETs MN1 and MN2 are turned off, and then the P-channel FETs MP1 and MP2 are turned on.
Therefore, in the limiter ON state, a limiter current ILIM flows as shown by a broken line in FIG.
At this time, the terminal voltage range VRNG of the output terminals AG1 and AG2 of the power generator AG is as follows:
VRNG = VDD ± (ILIM × RMPON)
It becomes.

Accordingly, the output of the comparator CMP1A and the output of the comparator CMP1B become “L” level in the AC cycle of the generated power, so that the power generation can be detected.
[6] Sixth Embodiment The sixth embodiment is an embodiment in which a power storage amount indicator function for displaying a charged amount is realized using a power generation detection circuit.
FIG. 12 shows a schematic configuration block diagram of the sixth embodiment. 12, the same parts as those in FIG. 2 are denoted by the same reference numerals.
The timekeeping device 1A according to the sixth embodiment includes a power generation unit 101 that generates AC power, and a limiter circuit 130 that prevents an excessive voltage due to the AC power generated by the power generation unit 101 from being applied to a subsequent circuit. A rectifier circuit 131 that converts an alternating current into a direct current, a power storage device 104 that stores the rectified power, and a power storage device 104 in the power generation unit 101 based on the power generation state of the power generation unit 101 and the operation state of the limiter circuit 130. A power generation detection circuit 102 that detects whether or not chargeable power generation is being performed and outputs power generation detection data DDT, a voltage detection circuit 132 that detects the storage voltage of the power storage device 104, and a reference oscillation circuit such as a quartz oscillator. An oscillation circuit 134 that oscillates a reference pulse having a stable frequency using the source 133, and a frequency division pulse obtained by dividing the reference pulse and a reference pulse are synthesized. A frequency divider circuit 135 that generates pulse signals having different pulse widths and timings, for example, a reference clock signal SCK, and a timing control that operates with electric energy stored in the power storage device 104 and outputs a motor drive pulse to perform timing control A circuit 105; a motor drive circuit 109 for outputting a drive signal for actually driving the pulse motor 10 based on the motor drive pulse; an external input device 136 for the user to issue various instructions; A power storage amount counter 137 implemented as an up / down counter for counting the amount of power storage for notifying a user of the amount of power storage of the power storage device 104 based on the clock signal SCK.

In this case, the power generation detection data DDT corresponds to, for example, the original power generation detection data DDET10 shown in FIG.
Hereinafter, an operation for realizing the charged amount indicator function will be described.
When power is generated by the power generation unit 101, the power generation detection circuit 102 determines whether or not power generation capable of charging the power storage device 104 is performed based on the power generation state of the power generation unit 101 and the operation state of the limiter 130 circuit. The power generation detection data DDT having a frequency corresponding to the cycle is output to the storage amount counter 137.
On the other hand, when the oscillation circuit 134 oscillates a reference pulse having a stable frequency using the reference oscillation source 133, the frequency divider 135 generates a reference pulse based on the divided pulse obtained by dividing the reference pulse and the reference pulse. A clock signal SCK is generated and output to the charged amount counter 137.
As a result, the charged amount counter 137 counts up based on the power generation detection data DDT and counts down based on the reference clock signal SCK, and the count value is proportional to the charged amount.

That is, the count value increases when the amount of charge to the power storage device is large, and decreases when the amount of charge is large (= proportional to the driving time of the timer).
As a result, by operating the external input device 136, it is possible to notify the user of the charged amount by, for example, holding the second hand at the fast-forward moving amount of the second hand or holding the second hand at the charged amount display position for a predetermined time. It becomes.
It should be noted that the present invention is not limited to the above-described power storage amount notification method, and may be configured to include a power storage amount indicator that constantly displays the power storage amount corresponding to the count value of the power storage amount counter 137.

[7] Effects of Embodiment According to each of the above embodiments, the state of charge can be reliably detected in accordance with the actual state of charge.
Therefore, countermeasures against adverse effects on the motor drive due to the electromagnetic noise level generated from the power generation unit (generator) during charging, and adverse effects on the circuit operation due to the power supply voltage fluctuation due to the generated current due to the internal resistance of the secondary battery, It can be performed only at the time of a large current where the adverse effect is likely to occur, that is, only at the time of power generation in which a chargeable current flows, thereby suppressing an increase in current consumption due to excessive measures and extending the drive time of the electronic device. be able to.
Further, the configuration of each of the above embodiments is a configuration for detecting the generated voltage, and can detect the generated current without affecting the charging performance, such as inserting a resistor in the charging path. Unlike the power generation detection method having the configuration described above, the power generation detection operation does not cause a decrease in the charging performance, so that the detection can be always performed.

[8] Modification of Embodiment [8.1] First Modification In the above-described embodiment, a timekeeping device that performs time display by driving an analog hand is described as an example. Needless to say, the present invention can also be applied to a digital clock device that performs the operation.

[8.2] Second Modification In the above embodiment, the wristwatch-type timepiece 1 was described as an example. However, the present invention is not limited to this, and other than a wristwatch, a portable pocket watch, The present invention can be applied to a non-portable table clock or a wall clock.

[8.3] Third Modification In the above embodiment, as the power generation device 40, an electromagnetic force that transmits the rotational motion of the rotary weight 45 to the rotor 43 and generates an electromotive force Vgen in the output coil 44 by the rotation of the rotor 43. Although a power generator is employed, the present invention is not limited to this. For example, a rotating motion is generated by a restoring force (corresponding to the first energy) of the mainspring, and an electromotive force is generated by the rotating motion. A power generating device or a power generating device that generates electric power by a piezoelectric effect by applying external or self-excited vibration or displacement (corresponding to first energy) to a piezoelectric body may be used.
Further, a power generation device that generates electric power by photoelectric conversion using light energy (equivalent to first energy) such as sunlight may be used.
Furthermore, a power generation device that generates electric power by thermal power generation using a temperature difference (thermal energy; corresponding to the first energy) between a certain part and another part may be used.
Further, it is also possible to receive an electromagnetic wave generated by receiving a floating electromagnetic wave such as a broadcast wave or a communication radio wave and use the energy (corresponding to the first energy).

[8.4] Fourth Modification In the above embodiment, the reference potential (GND) is set to Vdd (high potential side), but the reference potential (GND) may be set to VTKN (low potential side). Of course.

[8.5] Fifth Modified Example In each of the above-described embodiments, the power generation is detected to prevent an adverse effect on the electronic device due to the power generation. It is also possible to perform control.
For example, in an electronic device having a normal operation mode and a power saving operation mode as operation modes, when power generation is detected by the power generation detection device of each of the above embodiments, the operation mode is shifted to the normal operation mode, and power generation detection is performed. If power generation is not detected by the device, the operation mode may be changed to the power saving operation mode.

It is a figure showing the schematic structure of the clock device concerning the embodiment of the present invention. FIG. 3 is a functional block diagram of a control unit and its peripheral configuration according to the embodiment. FIG. 2 is a configuration diagram of a power generation detection circuit according to the first embodiment. 6 is an operation flowchart of the embodiment. It is a block diagram of the electric power generation detection circuit of 2nd Embodiment. It is a lineblock diagram of a power generation detection circuit of a 3rd embodiment. FIG. 3 is a diagram illustrating an example of a smoothing circuit. 13 is an operation timing chart of the third embodiment. FIG. 10 is a configuration diagram of a fourth embodiment liquid power generation detection circuit. 13 is an operation timing chart of the fourth embodiment. It is a schematic structure block diagram of a 5th embodiment. It is a schematic structure block diagram of a 6th embodiment. FIG. 3 is a detailed configuration diagram of a comparator according to the first embodiment. It is a detailed lineblock diagram of a comparator in a 2nd embodiment. It is a detailed lineblock diagram of a comparator in a 4th embodiment. It is explanatory drawing of embodiment when performing a half-wave rectification.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 ... Time measuring device 23 ... Control circuit 24 ... Drive control circuit 30S ... Second hand drive unit 30HM ... Hour and minute hand drive unit 40 ... Power generation device 45 ... Rotating weight 104 ... Power storage device (large capacity capacitor)
113: step-up / step-down circuit 90: mode setting section 91: power generation state detection section 93: central control circuit 94: mode storage section 95: set value switch 97: power generation detection circuit 98 ... second detection circuit 101: power generation section 102, 102A, 102B, 102C ... power generation detection circuit

Claims (7)

A power storage device that stores electric energy obtained by converting the first energy in a power generation device having a pair of output terminals,
A comparing unit that compares a voltage of an output terminal of the power generation device with a predetermined voltage corresponding to a terminal voltage of the power storage device, and outputs a comparison result signal;
Power generation detecting means for outputting a power generation detection signal corresponding to a state in which a generated current can flow when the voltage of the output terminal exceeds the terminal voltage of the power storage device based on the comparison result signal,
The power generation detection circuit, wherein the comparing means compares a voltage obtained by offsetting one of the two input voltages by a predetermined amount and the other voltage. Detecting whether or not the power storage device that stores the electric energy obtained by converting the first energy in the power generation device that is the AC power generation device having the first output terminal and the second output terminal is in a power generation state in which the power storage device can be charged. Power generation detection circuit
First comparing means for comparing a first output terminal voltage, which is a terminal voltage of the first output terminal, with a predetermined voltage corresponding to a terminal voltage of the power storage device, and outputting a first comparison result signal;
Second comparing means for comparing a second output terminal voltage, which is a terminal voltage of the second output terminal, with a predetermined voltage corresponding to a terminal voltage of the power storage device, and outputting a second comparison result signal;
Based on the first comparison result signal and the second comparison result signal, power generation is detected in a state where a generated current can flow when the first output terminal voltage or the second output terminal voltage exceeds the terminal voltage of the power storage device. Power generation detection means for outputting a signal,
The power generation detection circuit, wherein the comparing means compares a voltage obtained by offsetting one of the two input voltages by a predetermined amount and the other voltage. In a power generation detection circuit that detects a power generation state in which a power storage device that stores electric energy obtained by converting the first energy in the power generation device can be charged,
A step-up power storage device connected to one output terminal of the power generation device,
Comparing means for comparing a storage voltage of the boosting power storage device with a predetermined voltage corresponding to a terminal voltage of the power storage device, and outputting a comparison result signal;
Power generation detecting means for outputting a power generation detection signal corresponding to a state in which a generated current can flow when the output terminal voltage exceeds a predetermined voltage corresponding to a terminal voltage of the power storage device based on the comparison result signal. ,
The power generation detection circuit, wherein the comparing means compares a voltage obtained by offsetting one of the two input voltages by a predetermined amount and the other voltage. A power generator for converting the first energy into electrical energy;
A power storage device for storing the electric energy,
Driven means driven by the electric energy stored in the power storage device,
An electronic device comprising: the power generation detection circuit according to claim 1. A voltage at an output terminal of the power generation device having a pair of output terminals is compared with a predetermined voltage corresponding to a terminal voltage of the power storage device that stores electric energy obtained by converting the first energy in the power generation device. A comparison process;
A power generation detection step of detecting that, when the output terminal voltage exceeds the terminal voltage of the power storage device, the output terminal voltage corresponds to a state in which a generated current can flow, based on a result of the comparison in the comparison step;
With
The power generation detection method according to claim 1, wherein the comparing step compares a voltage obtained by offsetting one of the two input voltages by a predetermined amount and the other voltage. In a power generation detection method for detecting a power generation state of a power generation device that is an AC power generation device having a first output terminal and a second output terminal,
A first output terminal voltage that is a terminal voltage of the first output terminal, and a predetermined voltage corresponding to a terminal voltage of a power storage device that stores electric energy obtained by converting the first energy in the power generation device. A first comparing step of comparing;
A second comparing step of comparing a second output terminal voltage that is a terminal voltage of the second output terminal with a predetermined voltage corresponding to a terminal voltage of the power storage device;
When the first output terminal voltage or the second output terminal voltage exceeds the terminal voltage of the power storage device based on a result of the comparison in the first comparison step and the second comparison step, the state corresponds to a power generation state. And a power generation detection step of detecting
The power generation detection method according to claim 1, wherein the comparing step compares a voltage obtained by offsetting one of the two input voltages by a predetermined amount and the other voltage. A predetermined voltage corresponding to a terminal voltage of a power storage device that stores electric energy obtained by converting the first energy in the power generation device via a boosting power storage device connected to one output terminal of the power generation device; A comparing step of comparing the storage voltage of the boosting power storage device,
A power generation detection step of detecting that, when the output terminal voltage exceeds a predetermined voltage corresponding to the terminal voltage of the power storage device, the output terminal voltage corresponds to a state in which a generated current can flow, based on a result of the comparison,
The power generation detection method according to claim 1, wherein the comparing step compares a voltage obtained by offsetting one of the two input voltages by a predetermined amount and the other voltage.

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