JPS5841556B2 - Repeated signal status determination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a repetitive signal state determining circuit for determining the signal state of a repetitive signal such as an alternating current signal or a clock pulse.

For example, liquid crystal display devices in electronic watches are driven with alternating current to extend the life of the liquid crystal as much as possible.

This is because liquid crystals deteriorate significantly when a unidirectional voltage is applied for a long period of time.
Since a clock is generated at a frequency of kHz and supplied to the frequency divider circuit and the timekeeping calculation section, this clock is used to drive the liquid crystal display device with alternating current.

However, in electronic watches, the crystal oscillator attached externally to the integrated circuit may come off due to external impact, and in this case, if the liquid crystal display device is driven by DC, the liquid crystal will deteriorate, so the generation status of clock pulses must be monitored. There was a need.

This invention was made in view of the above circumstances, and determines whether or not a clock pulse or an AC signal is supplied as a signal to be determined, and determines whether the determination result is 1" (high level) or 0 (
It is an object of the present invention to provide a circuit for determining the state of a repetitive signal that outputs signals of different logic levels such as low level).

The present invention will be described in detail below with reference to the drawings.

In FIG. 1, 1 is a clock input terminal connected to a circuit that generates a signal to be determined, such as an oscillation circuit section of a clock circuit, 2 is an inverter circuit that inverts the signal to be determined that is supplied to this input terminal 1, and 3 is an inverter circuit that inverts the signal to be determined that is supplied to this input terminal 1. A capacitor 4 for removing DC components from the output signal of the inverter circuit 2 is an n-channel MOS transistor that is turned on and off by a clock pulse applied to the clock input terminal 1.

Further, 5 is an n-channel MO8) transistor whose gate electrode is connected to the connection point between the MOS transistor 4 and the capacitor 3, and 6 is the MOS transistor provided between the drain electrode of this MO8I transistor 5 and the power supply +V. 4 is a P-channel MOS transistor whose gate electrode is connected to the connection point between capacitor 3 and γ is the drain of this MOS transistor 6.

A capacitor connected in parallel between the sources; 8 an inverter circuit for detecting the voltage at the series connection point of both MOS transistors 5 and 6 to obtain a judgment signal; 9 a signal for extracting this judgment signal. It is a deba terminal.

Next, the operation of the determination circuit in the above embodiment will be explained with reference to the signal waveform diagram in FIG.

Now, clock input terminal 1 has a duty of 50% and 32
Assume that a kHz clock pulse is supplied.

When this clock pulse rises from a low level to a high level, on the contrary, the output of the inverter circuit 2 falls from a high level to a low level.

At this time, the voltage on the MO8t side of the capacitor 3 and the gate electrode side of the transistors 5 and 6 tends to have a negative polarity lower than the ground voltage, but the n-channel MOS transistor 4 is turned on by the clock pulse that becomes high level at this time. Therefore, the gate input voltages of MOS transistors 5 and 6 are set to a low voltage.

On the other hand, when the clock pulse falls from a high level to a low level, contrary to the above, the output of the inverter circuit 2 rises from a low level to a high level.

At this time, the n-channel MO8+- transistor 4 is turned off, and the voltage on the gate electrode side of the MO8I- transistors 5 and 6 of the capacitor 3 is set to a high voltage by the AC component passing through the capacitor 3.

At this time, the n-channel MO transistor 4 is in an off state, but a slight leakage current flows, so the high voltage gradually decreases.

Therefore, when the clock pulse is repeating high level and low level sequentially, the MOS transistor 5,
The gate input of 6 is as shown in FIG.

On the other hand, when the circuit threshold level of the CMOS inverter circuit consisting of MOS transistors 5 and 6 is VTl in FIG. 6 is non-conductive and in an off state.

Therefore, at this time, the input of the inverter circuit 8 is a MOS
It is set to a low level by transistor 5, and its output, ie, the decision signal, is set to a high level.

Further, when the MOS transistor 5 is in the on state, the capacitor 7 is charged by the power supply voltage +V so that the +V side thereof has a high potential.

When the clock pulse rises, the input voltage of the gate electrodes of MOS transistors 5 and 6 becomes a low voltage as described above, so MOS transistor 5 becomes non-conductive and turns off in synchronization with the rise of the clock pulse. , also MO
The S transistor 6 becomes conductive and turns on.

At this time, the charge in the capacitor 7 that has been charged up to now is discharged with a predetermined time constant via the MOS transistor 6 which is in the on state, so the input voltage of the inverter circuit 8 suddenly rises to a high level. Instead, it increases sequentially with the above-mentioned time constant as shown in the figure.

As long as a clock pulse whose voltage level fluctuates repeatedly is supplied to the clock input terminal 1, the input voltage of the inverter circuit 8 will not become higher than the threshold level VT2 of the inverter circuit 8, and the signal output terminal 9 will not exceed the threshold level VT2 of the inverter circuit 8. High) Novel signal continues to be output.

By the way, next we will explain the case when the clock pulse is no longer supplied to the clock input terminal 1.

At this time, the level when the supply of the clock pulse is stopped may be a high level (indicated by a broken line) or a low level (indicated by a solid line).

First, if the clock pulse stops at a high level, M
Since the OS transistor 4 remains on, the MO
The input voltage of the gate electrodes of the S transistors 5 and 6 becomes a low voltage, the MO8+- transistor 5 is turned off, and the MOS transistor 6 is turned on.

Then, the input voltage of the inverter circuit 8 gradually increases to a high level, and when it exceeds VT2, the output of the inverter circuit 8 is inverted to a low level.

Furthermore, if the clock pulse stops at a low level, immediately after the clock pulse stops, the AC component that has passed through the capacitor 3 causes the MO
The gate input voltages of S transistors 5 and 6 are set to high voltages.

However, as mentioned above, the voltage gradually decreases due to the leakage current of the MOS transistor 4, and its value becomes VTt.
When the voltage becomes lower than , the MOS transistor 6 turns on, and the input voltage of the inverter circuit 8 gradually increases to a high level similarly to the above.

When the input voltage of the circuit 8 exceeds VT2, the output of the inverter circuit 8 is inverted to a low level.

In this way, no matter at which level the clock pulse stops, the signal level applied to the signal output terminal 9 will be low.

Note that when the clock pulse is supplied, the input voltage of the inverter circuit 8 reaches its threshold level VT.
It is necessary to adjust the time constant, which is determined by the on-resistance of the P-channel MOS transistor 6 and the capacitance value of the capacitor 7, so that it does not reach 2.

In this way, when a clock pulse whose level alternately fluctuates is supplied as a signal to be determined, the signal output is maintained at the first level, that is, a high level, and when there is no clock pulse, the signal output is at a second level, that is, a low level. is maintained.

At this time, the gate input resistance of MOS transistor 5 and ! Since the off-resistance of the 1-channel MOS transistor 4 is extremely high and the on-resistance of the P-channel MOS transistor 6 can be made high, it is not necessary to increase the capacitance of the capacitors 3 and 7, which is convenient when forming them in an integrated circuit.

FIG. 3 shows another embodiment of the present invention, in which a P-channel MOS transistor 4 is used in place of the n-channel MOS transistor 4. In FIG.

This case differs from the embodiment shown in FIG. 1 in that the judgment output is at a low level when there is a clock input, and at a high level when there is no clock input and the signal to be judged is at DC level. , have substantially the same effects, and corresponding parts are given the same reference numerals and their explanation will be omitted.

The above embodiments are all designed to detect the stoppage of oscillation of clock pulses in order to prevent deterioration of the liquid crystal in a liquid crystal display device. It can also be used effectively for detecting general alternating current signals such as sine waves.

As described above, according to the present invention, the clock pulse,
The signal state can be determined using an AC signal as the signal to be determined,
A determination circuit capable of outputting determination results as signals of different logic levels can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the invention, FIG. 2 is an operation waveform diagram of the same embodiment, and FIG. 3 is a circuit diagram showing another embodiment of the invention. 1... Clock input terminal, 2... Inverter circuit, 3... Capacitor, 4...
・MOS transistor, 5...MOS transistor, 6...MO8t-transistor, 7...
... Capacitor, 8 ... Inverter circuit, 9
...Signal output terminal.

Claims (1)

[Claims] 1. An inverter to which the signal to be determined is input, a first capacitor for DC blocking whose - end is connected to the output terminal of this inverter, and a capacitor between the other end of this first capacitor and the first - potential point. a first channel type MO8+- transistor inserted and having its gate supplied with the signal to be determined;
a second MOS transistor of one channel type and a third MOS transistor of the other channel type, which are inserted in series between a first potential point and a second potential point, and whose respective gates are both connected to the other end of the first capacitor; 3rd M0 above
A second capacitor connected in parallel between the drain and source of the S transistor, and means for detecting the voltage at the series connection point of the second and third M0S transistors and outputting a determination signal. This circuit determines the state of a repetitive signal.