JPS6315560B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and more particularly to an electronic timepiece using a lithium battery or the like which has relatively high voltage and high internal resistance.

An object of the present invention is to provide a power supply that absorbs fluctuations in the voltage applied to the circuit due to fluctuations in battery voltage during heavy loads such as alarms and buzzers, and supplies a stable constant voltage to the clock circuit even when the battery voltage fluctuates. The object of the present invention is to provide an electronic timepiece with stable performance even under heavy loads by providing a circuit.

In recent years, the performance of lithium batteries has improved, and some of them have begun to be used in watches, and due to the recent high price of silver, lithium batteries are attracting attention as batteries for watches.

Lithium batteries usually have a voltage of 3V to 2.8V,
The battery capacity of a watch battery is 60 to 100 m at 3V.
It is AH. Complementary MOS-ICs for wristwatches operate sufficiently at 1.5V, so a voltage that is half the battery voltage (approximately 1.5V) is created by switching between two capacitors in series and parallel, and this voltage is used for watches.
It is well known that driving an IC can extend the battery life of a watch. Such a method and
Due to the low self-discharge rate of lithium batteries, it is possible to create wristwatches with a battery life of 5 to 7 years, but a major drawback to practical use is the high internal resistance of lithium batteries. There is. In particular, thin and small lithium batteries have high internal resistance and cannot be used in wristwatches with lamps or alarms.

In view of this, the present invention provides a power supply circuit that supplies a stable constant voltage to a timepiece circuit even if the battery voltage fluctuates during heavy loads such as lamps and buzzers.

The first part describes the structure of the electronic timepiece according to the present invention.
In the block diagram, 1 is a time standard source such as a crystal oscillator, 2 is a binary frequency divider circuit, and 3 is a time standard source such as a crystal oscillator.
is a counter circuit for seconds, minutes, hours, etc.; 4 is a decoder/display drive circuit; 5 is a display means such as a liquid crystal panel; 6 is a control circuit that receives signals from operation switches 14 to 17 and controls the clock circuit; 7 is a heavy load circuit such as a lamp, alarm, buzzer, etc., 11
is the power battery. Here, assuming that the power supply battery 11 is a lithium battery and its voltage is 3V, V _DD = OV,
Assuming that V _SS2 = −3V and V _SS1 = approximately −1.5V, V _DD , V _SS2 ,
The V _SS1 power supply line is shown as a dotted line. The solid lines in FIG. 1 are signal lines. 10 is a step-down circuit that switches the step-down capacitors 12 and 13 between series and parallel switching to step down the battery voltage to 1/2;
is a constant voltage circuit that outputs a constant voltage even if the voltage of the power supply battery 11 fluctuates, and this voltage is set to a value close to the output voltage of the step-down circuit, that is, 1/2 of the battery voltage, 15V. ing. Reference numeral 9 denotes a power supply control circuit, which normally stops the operation of the constant voltage circuit 8, operates the step-down circuit 10, and supplies the step-down voltage of the step-down circuit as the V _SS1 voltage. On the other hand, the lamp
When the heavy load circuit 7 is in operation, such as when ON, the power supply control circuit 9 stops the operation of the step-down circuit 10, operates the constant voltage circuit 8, and changes the stabilized voltage of the constant voltage circuit output to V _SS1 voltage. Supply as.

The reason why the constant voltage circuit 8 is always operated and the stabilized voltage of the constant voltage output is not supplied as V _SS1 regardless of the presence or absence of a heavy load is that the voltage drop of the constant voltage circuit 8 is This is because the loss is larger. That is, the step-down circuit 10 steps down the voltage by switching the capacitors 12 and 13 in series/parallel, so there is almost no step-down loss, but the constant voltage circuit 8 steps down the voltage by using the voltage drop of the MOS/TR as described later. However, since a stabilized voltage is obtained, the step-down loss is relatively large. Therefore, in normal times,
V _SS1 power is supplied by a step-down circuit 10 with high step-down efficiency, and the constant voltage circuit is operated only during heavy loads when it is necessary to stabilize the voltage, and the stabilized voltage is supplied as the V _SS1 power.

82 in FIG. 1 is a timer circuit, and it takes some time for the battery voltage to recover after the heavy load is removed.
After the heavy load is released, the constant voltage circuit 8 continues to operate only during the timer time. 84 in the same figure is a clock stop detection circuit. When the power supply control circuit 9 is stabilized in the state in which the step-down circuit 10 is operated when the battery is turned on, the step-down circuit clock 1024Hz is not present, so the step-down output is not output, and therefore the V _SS1 voltage In order to prevent oscillation from starting continuously due to
84 is a circuit for detecting the presence or absence of a 1024 Hz clock. When this circuit detects that the clock has stopped, the constant voltage circuit 8 is forcibly operated by the action of the power supply control circuit 9, and the V _SS1 power supply is secured. The constant voltage circuit 8 is configured to operate without the need for a clock, as will be described later.

FIG. 2 shows voltage waveforms related to the main power supply according to the block diagram of FIG. 1. A lithium battery is used as the power supply battery 11, and the open circuit voltage is
3V, battery internal resistance is 50 to 80Ω at room temperature, -10℃
Performance is around 150-200Ω. The heavy load is the lamp current. The left side of the vertical dotted line in Figure 2 is at room temperature;
The right side of the diagram shows the voltage waveforms of various parts at low temperatures.

In the figure, Sm is the lamp signal (17Sw ₄ in Figure 1), Sn is the output voltage of the lithium battery 11, So is the output voltage of the step-down circuit 10 in Figure 1, Sp is the output voltage of the constant voltage circuit 8, and Sq is the power supply control circuit. 9 output voltage. Sn
~Sq is a voltage waveform based on V _DD , and for convenience of explanation, the step-down circuit output So and the constant voltage circuit output Sp describe the output voltage when continuous operation is performed regardless of the presence or absence of a heavy load.

As is clear from Sn in the same figure, the battery voltage is around 2V at room temperature during the lattice pump current, and at low temperature.
The voltage drops to around 1.3V. Moreover, this is the voltage when about 150Ω is inserted in series with the lamp in order to reduce the lamp rush current, and if no measures are taken, the voltage during this rush will fall below 1V.

On the other hand, if the capacitor step-down circuit is operated even when the lamp is on, the step-down output will be 1/2 of the battery voltage, so as is clear from the figure So, the step-down output will drop to about 0.6V at low temperatures. , the V _SS1 system circuit does not operate at this voltage. To cover this voltage drop, the step-down circuit output is used as the V _SS1 power supply under normal conditions, and the battery voltage is directly connected during heavy loads.
There is also a method to use V _SS1 power supply, but this method uses Sn
As is clear from the above, the battery voltage fluctuates significantly depending on the temperature, so V _SS1 increases accordingly under heavy loads.
The power supply will also fluctuate, which can cause malfunctions. Possible malfunctions include counting errors and resetting of the counter circuit due to sudden voltage fluctuations.Also, under heavy loads under relatively high temperature conditions, the battery voltage does not drop much and the voltage close to 3V may occur. Since it is supplied to the V _SS1 power supply, there is a risk that the crystal oscillation circuit will cause harmonic oscillation.

In comparison, the constant voltage circuit output is Sp
As is clear from the voltage waveform, the voltage remains constant as long as the battery voltage does not fall below the output setting voltage of the constant voltage circuit, and when the battery voltage falls below the setting voltage,
It is output directly as the battery voltage or as the output of the constant voltage circuit.

Therefore, as mentioned above, under normal conditions, the step-down circuit 10
If the power supply control circuit 9 is configured so that the output of the constant voltage circuit 8 is used as the V _SS1 power source and the output of the constant voltage circuit 8 is used as the V _SS1 power source during heavy loads, the voltage shown in Figure 2 Sq will be supplied as the V _SS1 power source. be done. In Sq, the solid line indicates that the output of the voltage down converter 10 is supplied, and the dashed line indicates that the output of the constant voltage circuit 8 is supplied. Sr is
It shows the time during which the constant voltage circuit 8 is operating, and Ss measures a certain period of time after the heavy load is released. It represents the time during which the timer circuit 82 is operating. Due to this timer operation, after the heavy load is removed and the power supply voltage is completely restored, the V _SS1 power supply shifts from constant voltage output to step-down output. In addition, at V _SS1 voltage Sq,
There are places where the voltage drops momentarily, but this is because the battery voltage has dropped below the constant voltage setting voltage, so as mentioned above, insert a resistor in series with the lamp. Alternatively, by taking measures such as selecting an appropriate lamp, it is possible to suppress the voltage to around 1.3V, which is a level that does not cause any practical problems.

As described above, under the control of the power supply control circuit 9, the capacitor step-down circuit 10 operates under normal conditions, and the V _SS1 power can be supplied with a step-down conversion step-down rate of close to 100%. When a load is applied or when a heavy load is released, the constant voltage circuit 8 and the timer circuit 82 operate, and a stable voltage can be supplied as the V _SS1 power source.

As an embodiment of the electronic time according to the present invention, a circuit diagram related to the power supply circuit is shown in FIG. 3, and its main timing chart is shown in FIG. 4.

In FIG. 3, the block 8 within the dotted line corresponds to the constant voltage circuit 8 in FIG. Furthermore, block 82 corresponds to timer circuit 82, and block 84 corresponds to clock stop detection circuit 84, respectively. Block 83 is part of power supply control circuit 9 and forms a delay circuit.

In Fig. 3, 18', 28 are P・MOS・
FET, only 25 is depletion type,
All others are enhancement types. 29～
37 is enhancement type N・MOS・
FET, 41 to 48 are switching gates,
It is conductive when the gate potential is high, and non-conductive when the gate potential is low.
Gates other than those mentioned above, Flip/Flop (F/F), are all composed of complementary MOS/FETs. 38,
39 is a capacitor with a built-in IC, 40 and 8
5 to 87 are resistors also built into the IC. 51
~61 is master-slave FF, 62 and 64 are slave type half FF, and 63 is master type half FF, all of which are master-slave FF.
When CLOOK=High, write state, slave is
When CLOCK=Low, it enters the writing state. In Figure 3, as external elements outside the IC, 17 is a lamp lighting (SW ₄ ), 78 is a lamp, 79 is an NPN transistor for alarm driving, 80 is an inductance, 81 is a piezoelectric element, and 12 and 13 are step-down capacitors. (approximately 0.1 μF).

In Fig. 3, the 1024Hz D signal is a signal obtained by delaying the 1024Hz signal by a time such as 1/32768 seconds or 1/16384 seconds, and using the 1024Hz and 1024Hz D signals, _the 66 ( _A2 )
Thus, a two-phase clock for a step-down circuit as shown in FIG. 4 is made. AND gates 67 (A ₃ ), 68 (A ₄ )
In this case, a signal indicating that a heavy load has been driven from the heavy load circuit is input to F ₁₁ and F ₁₂ of the timer circuit 82, and F ₁₂ becomes High, that is,
When the F ₁₂ Q output becomes Low, F ₁₂ is inverted from High and becomes Low, and the AND gates 67 and 6
8, that is, A ₃ and A ₄ , so the gate outputs of A ₃ and A ₄ are both configured to be low as shown in FIG. 4 A ₃ and A ₄ .

To explain the operation of the step-down circuit 10, A ₄ is High
(Figure 4 A ₄ shaded area) is N・MOS・FET35,
36 becomes conductive, and capacitor 12 (C _A )
and capacitor 13 (C _B ) in series, V _DD −
V Connected between _SS2 power supplies. Since C _A and C _B have the same capacity, a voltage obtained by dividing the battery voltage by half is applied to V _SS1 . On the other hand, A ₃ is Low (4th
In the case of figure A ₃ shaded area), P・MOS・FET26,
27 becomes conductive, and C _B becomes V _DD − similar to C _A.
Connected between V _SS1 and supplies charged charge to the V _SS1 system.

In Figure 4, A ₃ shaded area (C _A and C _B are parallel)
It can be seen that under normal conditions with no heavy load, the _A4 oblique part (C _A and C _B series) is alternately repeated at a 1024 Hz cycle and the voltage drops. The phase difference between A ₃ and A ₃ oblique portions and the step-down using the two-phase clock is due to the combination of transistors 26 and 35, or 27 and 36, 35 and 27, and 26 and 36. This is to prevent the transistor from becoming conductive and causing a short between the power supplies or a loss of charge in C _B. It has been experimentally confirmed that if a step-down circuit is driven by a single-phase clock without this improvement, a step-down loss current of 0.1 to 0.2 μA will occur, depending on the size of the step-down transistor.

On the other hand, when a heavy load such as a lamp is on, the step-down operation stops, as is clear from the shaded area _A3 in Figure 4.
C _A and C _B are connected in parallel between V _DD and V _SS1 , and function as a power supply backup capacitor for the V _SS1 system.

In addition, when a heavy load is turned on, C _A and C _B are instantly connected in parallel to V _SS1 , and due to the function of the delay circuit 83, the time required for the constant voltage circuit to stabilize after the heavy load is turned on is approximately 1 ms. The gap between is the charge of C _A and C _B.
V Supply _SS1 power. This is instantaneous when heavy load is turned on.
C _A and C _B are not connected in parallel, and C _A and C _B are connected between V _DD and V _SS2 .
If they are connected in series, a voltage drop as shown in Figure 2 So will be supplied to the V _SS1 power supply, causing malfunction.

Furthermore, in this embodiment, after the heavy load timer is turned off,
When transitioning from constant voltage output to step-down circuit operation, be sure to
The system starts with C _A and C _B connected in series, and is designed to minimize voltage fluctuations.

The block 83 which inputs the _F12 signal of the timer circuit 82 and delays it is a delay circuit having the above-mentioned function, and is shown in FIG. 4 as _F13Q and _F14Q .
It is delayed with respect to F ₁₂ Q and becomes the signal of A ₅ . F ₁₂ Q＝Low
In other words, the constant voltage circuit turns on due to F ₁₂ = High,
When A ₅ =High, the V _SS1 power is supplied from the constant voltage circuit side, and the delay relationship is clear from FIG. 4.

Block 82 is a timer circuit, which uses the 1Hz signal from _F10 as a clock, and normally the _F12 output is Low. When the lamp or alarm is turned on, and for about 1.5 seconds after the lamp or alarm is turned off, the clock stop detection circuit 8
Since a signal is input to the reset terminal of _F12 while the clock is determined to be stopped and for about 1.5 seconds after the clock is canceled, the _F12Q constant voltage circuit 8 is operated. Block 84 is a clock stop detection circuit, which detects when the oscillation and frequency division circuits stop operating due to heavy load or the like and, for example, a 1024 Hz signal is not output. And each point Sh, Si, Sj, Sk
The signals at and Se operate as shown in the timing chart of FIG. Same circuit output Sl
is low during normal operation and high when the clock is stopped.

Block 8 in Figure 3 is a constant voltage circuit, and its basic idea is based on the one described in Japanese Patent Application No. 156164-1982.
8, 19, 29, 30 constitute a reference voltage source,
MOS/FET20,31 with MOS/FET21,2
A bias circuit is formed to operate 4 at a constant current. MOS・FET21~23,32,33
A differential amplifier circuit is formed with MOS/FET
24 and 34 form an amplifier circuit. MOS・
FET25 is a TR for voltage control, and a depletion mode P/MOS/FET is used in worst follow so that self-feedback is applied. Resistors 85 to 87 are voltage dividing resistors for setting output voltage values.

The reference voltage source is the gate part of N・MOS・FET29
By doping Poly-Si with P impurity,
N-MOS-FET doped with N impurity
It is created by utilizing the difference in threshold voltage VTH of each transistor due to the difference in work function due to the difference in polarity of the gate electrode P and N between FET 19 and V _DD . The voltage difference between V _TH of FET29 and V _TH of FET 30,
Approximately 1V appears.

Here, assuming that the reference voltage is V _ST , the resistor voltage division ratio by resistors 85 to 87 is A, and the constant voltage circuit output voltage is V _SS1 , V _ST = A × V _SS1 , and feedback is applied to maintain balance. , the gate bias of the control FET 25 is automatically set. If V _ST is 1V and V _SS1 is 1.5V, which is equal to the step-down circuit output voltage, then A = 1/1.5.

In this embodiment, the clock stop detection circuit 8
4 determines that the clock has stopped, the switching gate 47 becomes conductive, the resistor voltage division ratio A decreases to 1/1.7, and V _SS1 becomes around 1.7V, which is slightly higher than the normal voltage. , the crystal oscillator circuit has been devised to improve its self-starting performance.

Furthermore, as the battery voltage drops under heavy loads, the effective driving voltage of the liquid crystal display element decreases, making it difficult to see the liquid crystal, so the constant voltage circuit output during heavy loads is intentionally set to a high value such as 1.7V. This can be set to increase the effective voltage for driving the liquid crystal to make it easier to see.
However, there is no change in contrast, and a slight DC component remains, but this is within a range that poses no practical problem.

As detailed above, according to the present invention, the lamp,
Even if the battery voltage fluctuates significantly during heavy loads such as alarms, a stable voltage can be supplied to the clock circuit.
Moreover, high step-down efficiency can be obtained under normal conditions, so
A clock system with long battery life and no malfunctions can be realized.

Although the embodiments have been explained using lithium batteries, the present invention is not limited to electronic watches using lithium batteries, but can also be applied to electronic watches using other batteries with relatively high voltage. The present invention is applicable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of an electronic timepiece according to the present invention. FIG. 2 is a diagram showing voltage waveforms related to main power sources in the block diagram of FIG. 1. FIG. 3 is a circuit diagram related to a power supply circuit in an embodiment according to the present invention. Figure 4 shows the third
Timing chart of each main part of the circuit diagram. FIG. 5 is a timing chart of the main parts of the clock stop detection circuit 84. 1... Crystal oscillator, 2... Frequency dividing circuit, 3... Counter, 4... Decoder, drive circuit, 5...
Display element, 6...control circuit, 7...heavy load circuit,
8... constant voltage circuit, 9... power supply control circuit, 10...
. . . step-down circuit, 82 . . . timer circuit, 84 . . . clock stop detection circuit.

Claims (1)

[Claims] 1 A power supply battery 11 and a capacitor switched between series and parallel under the control of a clock signal.
A step-down circuit 10 that steps down the voltage of a battery 1, a time standard source 1 that forms the clock signal, and a frequency divider circuit 2.
In an electronic watch comprising an electronic circuit that receives the step-down voltage of the step-down circuit 10, and a heavy-load circuit 7 such as a buzzer, lamp, etc. that receives voltage supply from the power supply battery 11, the drive signal of the heavy-load circuit 7 is a constant voltage circuit 8 which receives the drive signal and forms a constant voltage from the battery voltage; a delay circuit 83 which outputs a switching signal obtained by delaying the drive signal by a certain period of time; a power supply including first gate circuits 67, 68 for inhibiting clock signals and fixing the capacitors in parallel connection; and second gate circuits 48, 72 for receiving the switching signal and supplying the constant voltage to the electronic circuit; An electronic timepiece characterized by comprising a control circuit 9.