JPS5837718A - Power supply circuit - Google Patents

Abstract

PURPOSE:To stabilize a power supply voltage of a circuit unit even at load, by connecting a switch and a capacitor between the circuit unit consisting of an LSI and the like, a power supply and a load driving circuit. CONSTITUTION:A capacitor 11 is connected between a power supply voltage supply terminal V'ss of an LSI1 and ground Vdd, and a switch 12 is inserted to a DC voltage supply path between a connecting point of the capacitor 11 and the power supply voltage terminal of the LSI1 and a connecting point of a battery 2 and a load driving circuit 3. A clock phi and the frequency of a load driving signal A are matched. But the fall of the clock phi has a little delay than the fall of the signal A. At the fluctuation of a power supply Vss, the capacitor 11 is discharged to the LSI1, then the fluctuation of the Vss is not given to the LSI1, the V'ss is made constant to stably operate the LSI1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply circuit for supplying a stabilized power supply voltage to a circuit such as an L8I (Large Scale Integrated Circuit).

Generally, in L8I devices such as electronic watches and calculators, the power supply voltage often fluctuates when driving a load such as a buzzer. A conventional example of this type of power supply circuit is shown in FIG. In the figure, 1 is an LSI constituting a circuit unit, J is a battery as a DC power supply that supplies power supply voltage to this LSIJ, and 3 is a load drive circuit connected to this battery 2. It consists of a load 4 connected in series between VDD and Was, and a driving transistor 5, and this transistor 5 is driven by a load driving circuit from the LSIJ. This first
In the circuit shown in the figure, when the drive transistor 5 is turned on (conducted) and current flows to the load 4, the voltage Vss of the battery 1 drops, so the LSIJ that is operating at this Vmm may malfunction. fto, that is, in the case of an alarm watch in which the load 4 of the circuit shown in FIG. The present invention aims to provide a power supply circuit that can stabilize the power supply voltage of the circuit unit even when loaded by connecting a switch and a capacitor between the power supply and the load driving circuit.

An embodiment of the present invention will be described below with reference to the drawings. 1s
Figure 2 is a circuit diagram showing the same embodiment, and this circuit is
Since this is an example in which the circuit corresponds to the circuit shown in the figure, the same reference numerals are used for the corresponding parts, and the explanation will be omitted. The feature of the circuit shown in Fig. 2 is that a capacitor 11 is connected between the power supply voltage supply end (denoted by Vss') of the LSIJ and the ground (denoted by VDI), and a capacitor 11 is connected between the power supply voltage supply end of the LSIJ and the power supply voltage supply end of the LSIJ. This is the point where the switch 12 is inserted in the DC voltage supply path between the connection point between the battery 2 and the load drive circuit 3, and the connection point between the load drive signal A and the load drive circuit 3. The operating clock φ is set as 1 in FIG. 3 to match the frequency of this clock and the load drive signal A. However, the fall of the clock φ is slightly delayed from the fall of the signal M, and the swing f is started after Vs- returns to a stable level.
-12 is turned on to start charging the capacitor 11. The rise of the clock may be made slightly earlier than the rise of the load drive signal.

By setting K in this way, when the power supply Vs+s fluctuates, the capacitor 11 becomes discharged to the LSIJ, so Vs-
Fluctuations in Vsm' are no longer transmitted to the LSI 1, and therefore Vsm' is kept constant, allowing the LSI 1 to operate stably.

FIG. 4 shows an example in which the circuit shown in FIG. 2 is applied to an actual MO8 type L8I. Here, the switch 12 in FIG.
O8) is formed by a capacitor, and the clock φ is supplied to the gate of the transistor 12 via the inverter 21. However, the power supply of the inverter 21 is Vsa' - VDI
It is I.

As explained above, according to the present invention, when the power supply is stable, the capacitor is charged with the power supply voltage, and when the power supply fluctuates, the capacitor is discharged to the circuit unit, so that the power supply voltage of the circuit unit is stabilized from beginning to end. What the power supply circuit can provide is 0

[Brief explanation of the drawing]

Fig. 1 is a conventional power supply circuit diagram, Fig. 2 is a circuit diagram of an embodiment of the present invention, Fig. 3 is a timing waveform diagram showing the operation of the same port i, and Fig. 4 is a specific example of Fig. 2. FIG. 1...LSI (circuit unit), 2...Battery (DC power supply), 3...Load drive circuit, 4...Load, 5...
・Drive transistor, capacitor in 11, 12...
Switch ○ Figure 1

Claims (2)

[Claims] (1) A circuit unit, a DC power supply that supplies a power supply voltage to this circuit unit, a load drive circuit connected to this power supply and the circuit unit, a capacitor connected to the power supply voltage supply end of the circuit unit, and this an rt+ switch inserted in a power supply voltage supply terminal between a connection point between a capacitor and a power supply voltage supply terminal of the circuit unit and a connection point between the DC power supply and the load drive circuit; A power supply circuit characterized in that the switch is opened when the load drive circuit is driven, and the switch is closed when the load drive circuit is not driven. (2) The power supply circuit 0 according to claim 1, wherein the closing timing of the switch is after a period required for stabilization of the DC power supply voltage has elapsed.