JPS56162831A - Forming method for electrode and wiring layer - Google Patents

Forming method for electrode and wiring layer

Info

Publication number
JPS56162831A
JPS56162831A JP6751680A JP6751680A JPS56162831A JP S56162831 A JPS56162831 A JP S56162831A JP 6751680 A JP6751680 A JP 6751680A JP 6751680 A JP6751680 A JP 6751680A JP S56162831 A JPS56162831 A JP S56162831A
Authority
JP
Japan
Prior art keywords
layer
aluminum
oxidized
aluminum layer
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6751680A
Other languages
Japanese (ja)
Inventor
Teruhiko Yamazaki
Yoshimare Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6751680A priority Critical patent/JPS56162831A/en
Publication of JPS56162831A publication Critical patent/JPS56162831A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form a fine electrode wiring layer by forming a predetermined pattern of photosensitive resin layer on an aluminum layer having an oxidized aluminum layer on the surface on a semiconductor and plasma etching the oxidized aluminum and the aluminum under the resin layer. CONSTITUTION:An aluminum layer 4 is formed through an Si oxidized film 3 on a semiconductor substrate 1 having a semiconductor active region 2, an oxidized aluminum layer 5 is formed on the surface by an anodic oxidation or the like, a photosensitive resin layer (AZ-1350 or the like) 6 is then formed in a predetermined pattern, is etched in the plasmatic atmosphere of gas containing a composition of CCl4:N2:O2=1:2:7 under reduced pressure, and the oxidized aluminum layer and the aluminum layer are removed under the layer 6. Thus, it can form the microminiature pattern peculiar for a dry etching withiout occurring an undercut phenomenon.
JP6751680A 1980-05-19 1980-05-19 Forming method for electrode and wiring layer Pending JPS56162831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6751680A JPS56162831A (en) 1980-05-19 1980-05-19 Forming method for electrode and wiring layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6751680A JPS56162831A (en) 1980-05-19 1980-05-19 Forming method for electrode and wiring layer

Publications (1)

Publication Number Publication Date
JPS56162831A true JPS56162831A (en) 1981-12-15

Family

ID=13347221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6751680A Pending JPS56162831A (en) 1980-05-19 1980-05-19 Forming method for electrode and wiring layer

Country Status (1)

Country Link
JP (1) JPS56162831A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120782A (en) * 1976-04-05 1977-10-11 Nec Corp Manufacture of semiconductor device
JPS531198A (en) * 1976-05-14 1978-01-07 Int Plasma Corp Method of etching silicon dioxide

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120782A (en) * 1976-04-05 1977-10-11 Nec Corp Manufacture of semiconductor device
JPS531198A (en) * 1976-05-14 1978-01-07 Int Plasma Corp Method of etching silicon dioxide

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