JPS56160048A - Mounting structure of integrated circuit - Google Patents

Mounting structure of integrated circuit

Info

Publication number
JPS56160048A
JPS56160048A JP6447480A JP6447480A JPS56160048A JP S56160048 A JPS56160048 A JP S56160048A JP 6447480 A JP6447480 A JP 6447480A JP 6447480 A JP6447480 A JP 6447480A JP S56160048 A JPS56160048 A JP S56160048A
Authority
JP
Japan
Prior art keywords
solder
mounting structure
bump
bonding
resists
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6447480A
Other languages
Japanese (ja)
Inventor
Hiroyuki Mabuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP6447480A priority Critical patent/JPS56160048A/en
Publication of JPS56160048A publication Critical patent/JPS56160048A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To perform a stabilized and highly reliable bonding as well as to contrive to miniaturize the subject mounting structure by a method wherein a solder bump and the solder resist as a spacer are provided on a circuit substrate and a bonding work is performed on an IC chip. CONSTITUTION:On the circuit substrate 7, four solder resists 11a consisting of photoresistive dry film are provided in such manner that a uniform thickness is given to the resists, the height of the bump is controlled and also the solder bump 9 is accurately positioned facing a pattern 14. On the solder resists 11a, the IC chip 8 is placed, fused by heating and a bonding work is performed. Through these procedures, the variation in the height of the bump is eliminated, while a highly reliable and stabilized bonding is performed and also the mounting structure can be miniaturized.
JP6447480A 1980-05-15 1980-05-15 Mounting structure of integrated circuit Pending JPS56160048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6447480A JPS56160048A (en) 1980-05-15 1980-05-15 Mounting structure of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6447480A JPS56160048A (en) 1980-05-15 1980-05-15 Mounting structure of integrated circuit

Publications (1)

Publication Number Publication Date
JPS56160048A true JPS56160048A (en) 1981-12-09

Family

ID=13259254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6447480A Pending JPS56160048A (en) 1980-05-15 1980-05-15 Mounting structure of integrated circuit

Country Status (1)

Country Link
JP (1) JPS56160048A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02226736A (en) * 1989-02-28 1990-09-10 Sony Corp Wiring board
WO2006024262A1 (en) * 2004-09-02 2006-03-09 Infineon Technologies Ag High-frequency module comprising filter structures and method for the production thereof
JP2007180166A (en) * 2005-12-27 2007-07-12 Seiko Epson Corp Electronic component, manufacturing method thereof, circuit board, and electronic equipment
JP2008060585A (en) * 1994-09-20 2008-03-13 Tessera Inc Method for forming compliant interface of semiconductor chip
US7878385B2 (en) * 2002-05-07 2011-02-01 Microfabrica Inc. Probe arrays and method for making
CN102543765A (en) * 2012-01-13 2012-07-04 迈普通信技术股份有限公司 Method for designing bonding pad of surface mounted component, bonding pad structure and printing circuit board

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02226736A (en) * 1989-02-28 1990-09-10 Sony Corp Wiring board
JP2008060585A (en) * 1994-09-20 2008-03-13 Tessera Inc Method for forming compliant interface of semiconductor chip
JP4708401B2 (en) * 1994-09-20 2011-06-22 テセラ・インコーポレーテッド Method for forming a compliant interface of a semiconductor chip
US7878385B2 (en) * 2002-05-07 2011-02-01 Microfabrica Inc. Probe arrays and method for making
WO2006024262A1 (en) * 2004-09-02 2006-03-09 Infineon Technologies Ag High-frequency module comprising filter structures and method for the production thereof
JP2007180166A (en) * 2005-12-27 2007-07-12 Seiko Epson Corp Electronic component, manufacturing method thereof, circuit board, and electronic equipment
CN102543765A (en) * 2012-01-13 2012-07-04 迈普通信技术股份有限公司 Method for designing bonding pad of surface mounted component, bonding pad structure and printing circuit board

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