JPS56158479A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56158479A
JPS56158479A JP6123480A JP6123480A JPS56158479A JP S56158479 A JPS56158479 A JP S56158479A JP 6123480 A JP6123480 A JP 6123480A JP 6123480 A JP6123480 A JP 6123480A JP S56158479 A JPS56158479 A JP S56158479A
Authority
JP
Japan
Prior art keywords
gate
fet30
electrode
source
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6123480A
Other languages
Japanese (ja)
Inventor
Nobuo Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6123480A priority Critical patent/JPS56158479A/en
Publication of JPS56158479A publication Critical patent/JPS56158479A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Protection Of Static Devices (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To prevent the breakdown of a gate without degrading frequency characteristics by connecting an MISFET between a gate electrode of the MISFET and an external input terminal so that a source region and a drain region are inserted. CONSTITUTION:On a substrate 20 wherein an MOSFET25 is provided, is formed an FET30 comprising a reverse conductive type source 27, a drain 28, and a gate electrode 26. Reverse conductive impurities are doped in a channel region 29 to the FET30, and a depression type is obtained. A source electrode 31 of said FET30 is connected to the external terminal 19, a drain electrode 32 is connected to the gate electrode 22 of the FET25, and the gate electrode 26 is connected to a base electrode 33. This circuit is constituted so that VB>VM>VA, where VB is a breakdown voltage of the gate 22, VM is a voltage at which the doped region 29 is completely depleted, and VA is avalanche starting voltage of a source junction 38. In this constitution, the FET30 operates as a nonlinear resistor, the frequency characteristics are not degraded, and the gate 22 is protected from the excessive input.
JP6123480A 1980-05-10 1980-05-10 Semiconductor device Pending JPS56158479A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6123480A JPS56158479A (en) 1980-05-10 1980-05-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6123480A JPS56158479A (en) 1980-05-10 1980-05-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56158479A true JPS56158479A (en) 1981-12-07

Family

ID=13165322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6123480A Pending JPS56158479A (en) 1980-05-10 1980-05-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56158479A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5079609A (en) * 1988-12-28 1992-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having dielectric breakdown protection element and method of fabricating same
GB2368456A (en) * 2000-04-03 2002-05-01 Nec Corp Electrostatic discharge protection circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5079609A (en) * 1988-12-28 1992-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having dielectric breakdown protection element and method of fabricating same
GB2368456A (en) * 2000-04-03 2002-05-01 Nec Corp Electrostatic discharge protection circuit
GB2368456B (en) * 2000-04-03 2003-06-25 Nec Corp Semiconductor device and method for manufacturing the same

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