JPS56158456A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS56158456A
JPS56158456A JP6176880A JP6176880A JPS56158456A JP S56158456 A JPS56158456 A JP S56158456A JP 6176880 A JP6176880 A JP 6176880A JP 6176880 A JP6176880 A JP 6176880A JP S56158456 A JPS56158456 A JP S56158456A
Authority
JP
Japan
Prior art keywords
layer
wiring
electrode
type
bump electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6176880A
Other languages
Japanese (ja)
Other versions
JPS6257101B2 (en
Inventor
Kohei Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6176880A priority Critical patent/JPS56158456A/en
Publication of JPS56158456A publication Critical patent/JPS56158456A/en
Publication of JPS6257101B2 publication Critical patent/JPS6257101B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent a short-circuit between a bump electrode and a wiring of the semiconductor element by a method wherein a gap is provided between an insulating film on the wiring having different potential and the bump electrode. CONSTITUTION:An Si substrate 1 having the prescribed diffusion layer is covered partially with an SiO2 layer 5, a wiring layer 8 for connection is provided on the N type layer 2 and a wiring 7 for the bump electrode is provided to connect between the P type layers 3, 4, and an Au layer 11 containing Sb is formed on the lower face of the substrate 1. An opening is formed in a CVDSiO2 layer 9, a bump type Ag19 is formed by plating on the exposed wiring layer 7 and Ag12 is adhered also on the lower face of the substrate 1. A wax 20 is applied up to the height of the Ag layer 19, plating is performed again and after a mushroom type bump electrode 10 is formed, the wax 20 is removed to complete the element. By this constitution, even when a crack is generated in the protective insulating film 9, because a short-circuit is not generated owing to a gap 17 between the circumference 21 of the electrode 10 and the wiring layer 8 having different potential from the electrode 10, breakdown strength by a large current is enhanced.
JP6176880A 1980-05-12 1980-05-12 Semiconductor element Granted JPS56158456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6176880A JPS56158456A (en) 1980-05-12 1980-05-12 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6176880A JPS56158456A (en) 1980-05-12 1980-05-12 Semiconductor element

Publications (2)

Publication Number Publication Date
JPS56158456A true JPS56158456A (en) 1981-12-07
JPS6257101B2 JPS6257101B2 (en) 1987-11-30

Family

ID=13180615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6176880A Granted JPS56158456A (en) 1980-05-12 1980-05-12 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS56158456A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54128669A (en) * 1978-03-29 1979-10-05 Nippon Denso Co Ltd Flip chip element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54128669A (en) * 1978-03-29 1979-10-05 Nippon Denso Co Ltd Flip chip element

Also Published As

Publication number Publication date
JPS6257101B2 (en) 1987-11-30

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