JPS56140459A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS56140459A
JPS56140459A JP4349680A JP4349680A JPS56140459A JP S56140459 A JPS56140459 A JP S56140459A JP 4349680 A JP4349680 A JP 4349680A JP 4349680 A JP4349680 A JP 4349680A JP S56140459 A JPS56140459 A JP S56140459A
Authority
JP
Japan
Prior art keywords
processors
common bus
master clock
machine cycle
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4349680A
Other languages
English (en)
Other versions
JPS6325381B2 (ja
Inventor
Yasushi Fukunaga
Tadaaki Bando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4349680A priority Critical patent/JPS56140459A/ja
Priority to US06/250,644 priority patent/US4523274A/en
Publication of JPS56140459A publication Critical patent/JPS56140459A/ja
Publication of JPS6325381B2 publication Critical patent/JPS6325381B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
JP4349680A 1980-04-04 1980-04-04 Data processing system Granted JPS56140459A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP4349680A JPS56140459A (en) 1980-04-04 1980-04-04 Data processing system
US06/250,644 US4523274A (en) 1980-04-04 1981-04-03 Data processing system with processors having different processing speeds sharing a common bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4349680A JPS56140459A (en) 1980-04-04 1980-04-04 Data processing system

Publications (2)

Publication Number Publication Date
JPS56140459A true JPS56140459A (en) 1981-11-02
JPS6325381B2 JPS6325381B2 (ja) 1988-05-25

Family

ID=12665315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4349680A Granted JPS56140459A (en) 1980-04-04 1980-04-04 Data processing system

Country Status (2)

Country Link
US (1) US4523274A (ja)
JP (1) JPS56140459A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593676A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd プロセツサ間クロツク同期化方式
JPS61217817A (ja) * 1985-03-23 1986-09-27 Fujitsu Ltd デ−タおよびタイミング信号入力回路

Families Citing this family (39)

* Cited by examiner, † Cited by third party
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US4677433A (en) * 1983-02-16 1987-06-30 Daisy Systems Corporation Two-speed clock scheme for co-processors
US4811052A (en) * 1985-08-08 1989-03-07 Canon Kabushiki Kaisha Control device for control of multi-function control units in an image processing apparatus
CA1270338A (en) * 1985-09-11 1990-06-12 Akihiko Hoshino Data processing system for processing units having different throughputs
US4888684A (en) * 1986-03-28 1989-12-19 Tandem Computers Incorporated Multiprocessor bus protocol
US5230067A (en) * 1988-05-11 1993-07-20 Digital Equipment Corporation Bus control circuit for latching and maintaining data independently of timing event on the bus until new data is driven onto
JPH01303543A (ja) * 1988-05-31 1989-12-07 Fujitsu Ltd メモリアクセス制御装置
US5261057A (en) * 1988-06-30 1993-11-09 Wang Laboratories, Inc. I/O bus to system interface
JPH06101043B2 (ja) * 1988-06-30 1994-12-12 三菱電機株式会社 マイクロコンピュータ
US5003463A (en) * 1988-06-30 1991-03-26 Wang Laboratories, Inc. Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
US5193193A (en) * 1988-09-14 1993-03-09 Silicon Graphics, Inc. Bus control system for arbitrating requests with predetermined on/off time limitations
US5201029A (en) * 1988-10-24 1993-04-06 U.S. Philips Corporation Digital data processing apparatus using daisy chain control
US5274784A (en) * 1989-01-13 1993-12-28 International Business Machines Corporation Data transfer using bus address lines
US5237676A (en) * 1989-01-13 1993-08-17 International Business Machines Corp. High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device
US5109490A (en) * 1989-01-13 1992-04-28 International Business Machines Corporation Data transfer using bus address lines
KR930001922B1 (ko) * 1989-08-28 1993-03-20 가부시기가이샤 히다찌세이사꾸쇼 데이터 처리장치
JPH0398145A (ja) * 1989-09-11 1991-04-23 Hitachi Ltd マイクロプロセッサ
GB9012970D0 (en) * 1989-09-22 1990-08-01 Ibm Apparatus and method for asynchronously delivering control elements with pipe interface
US5077686A (en) * 1990-01-31 1991-12-31 Stardent Computer Clock generator for a computer system
US5263172A (en) * 1990-04-16 1993-11-16 International Business Machines Corporation Multiple speed synchronous bus having single clock path for providing first or second clock speed based upon speed indication signals
US5247636A (en) * 1990-05-31 1993-09-21 International Business Machines Corporation Digital processor clock circuit
GB2252432B (en) * 1991-02-01 1994-09-28 Intel Corp Method and apparatus for operating a computer bus using selectable clock frequencies
JP3599334B2 (ja) * 1991-08-16 2004-12-08 マルティチップ テクノロジー， インコーポレイテッド 高性能ダイナミックメモリシステム
US5715407A (en) * 1992-03-06 1998-02-03 Rambus, Inc. Process and apparatus for collision detection on a parallel bus by monitoring a first line of the bus during even bus cycles for indications of overlapping packets
USRE39879E1 (en) * 1992-03-06 2007-10-09 Rambus, Inc. Method of transferring data by transmitting lower order and upper order memory address bits in separate words with respective op codes and start information
US5392422A (en) * 1992-06-26 1995-02-21 Sun Microsystems, Inc. Source synchronized metastable free bus
SE9203016L (sv) * 1992-10-14 1994-04-15 Ericsson Telefon Ab L M Signalbehandlingssystem med delat dataminne
JP2862471B2 (ja) * 1992-11-23 1999-03-03 モトローラ・インコーポレイテッド 電気回路
JPH06274463A (ja) * 1993-03-19 1994-09-30 Hitachi Ltd データ通信システム
JP3579461B2 (ja) * 1993-10-15 2004-10-20 株式会社ルネサステクノロジ データ処理システム及びデータ処理装置
US5566325A (en) * 1994-06-30 1996-10-15 Digital Equipment Corporation Method and apparatus for adaptive memory access
US5680594A (en) * 1995-05-24 1997-10-21 Eastman Kodak Company Asic bus interface having a master state machine and a plurality of synchronizing state machines for controlling subsystems operating at different clock frequencies
US5835970A (en) * 1995-12-21 1998-11-10 Cypress Semiconductor Corp. Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses
US6549593B1 (en) 1999-07-19 2003-04-15 Thomson Licensing S.A. Interface apparatus for interfacing data to a plurality of different clock domains
US6490638B1 (en) * 1999-08-23 2002-12-03 Advanced Micro Devices, Inc. General purpose bus with programmable timing
TW200416598A (en) * 2003-02-24 2004-09-01 Weltrend Semiconductor Inc Method for increasing the instruction execution speed of single chip microcomputer
CN100476694C (zh) * 2007-09-28 2009-04-08 中国科学院计算技术研究所 一种多核处理器及其变频装置和核间通信方法
EP2533022A1 (de) * 2011-06-10 2012-12-12 Hexagon Technology Center GmbH Hochpräzise synchronisierte Messwerterfassung
WO2021112710A1 (ru) * 2019-12-05 2021-06-10 Общество С Ограниченной Ответственностью "Научно-Технический Центр Мзта" Система автоматического конфигурирования модульного плк

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5173342A (ja) * 1974-12-21 1976-06-25 Hitachi Ltd
JPS5680759A (en) * 1979-12-06 1981-07-02 Casio Comput Co Ltd Control system for plural central processors

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513463B1 (ja) * 1970-09-25 1976-02-03
US3909791A (en) * 1972-06-28 1975-09-30 Ibm Selectively settable frequency divider
US4014006A (en) * 1973-08-10 1977-03-22 Data General Corporation Data processing system having a unique cpu and memory tuning relationship and data path configuration
US3950729A (en) * 1973-08-31 1976-04-13 Nasa Shared memory for a fault-tolerant computer
FR2406916A1 (fr) * 1977-10-18 1979-05-18 Ibm France Systeme de transmission de donnees decentralise
US4223380A (en) * 1978-04-06 1980-09-16 Ncr Corporation Distributed multiprocessor communication system
US4338599A (en) * 1978-07-21 1982-07-06 Tandy Corporation Apparatus for alpha-numeric/graphic display
US4229791A (en) * 1978-10-25 1980-10-21 Digital Equipment Corporation Distributed arbitration circuitry for data processing system
US4232366A (en) * 1978-10-25 1980-11-04 Digital Equipment Corporation Bus for a data processing system with overlapped sequences
US4281380A (en) * 1978-12-27 1981-07-28 Harris Corporation Bus collision avoidance system for distributed network data processing communications system
JPS5840214B2 (ja) * 1979-06-26 1983-09-03 株式会社東芝 計算機システム
US4442504A (en) * 1981-03-09 1984-04-10 Allen-Bradley Company Modular programmable controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5173342A (ja) * 1974-12-21 1976-06-25 Hitachi Ltd
JPS5680759A (en) * 1979-12-06 1981-07-02 Casio Comput Co Ltd Control system for plural central processors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593676A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd プロセツサ間クロツク同期化方式
JPS61217817A (ja) * 1985-03-23 1986-09-27 Fujitsu Ltd デ−タおよびタイミング信号入力回路

Also Published As

Publication number Publication date
JPS6325381B2 (ja) 1988-05-25
US4523274A (en) 1985-06-11

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