JPS56137632A - Pattern forming - Google Patents
Pattern formingInfo
- Publication number
- JPS56137632A JPS56137632A JP4089980A JP4089980A JPS56137632A JP S56137632 A JPS56137632 A JP S56137632A JP 4089980 A JP4089980 A JP 4089980A JP 4089980 A JP4089980 A JP 4089980A JP S56137632 A JPS56137632 A JP S56137632A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- space
- regist
- resists
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4089980A JPS56137632A (en) | 1980-03-28 | 1980-03-28 | Pattern forming |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4089980A JPS56137632A (en) | 1980-03-28 | 1980-03-28 | Pattern forming |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56137632A true JPS56137632A (en) | 1981-10-27 |
JPS6310891B2 JPS6310891B2 (enrdf_load_stackoverflow) | 1988-03-10 |
Family
ID=12593351
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4089980A Granted JPS56137632A (en) | 1980-03-28 | 1980-03-28 | Pattern forming |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56137632A (enrdf_load_stackoverflow) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6010624A (ja) * | 1983-06-29 | 1985-01-19 | Mitsubishi Electric Corp | パタ−ン形成方法 |
US5981114A (en) * | 1993-11-16 | 1999-11-09 | Nec Corporation | Photoresist check patterns in highly integrated circuits having multi-level interconnect layers |
US6979860B2 (en) * | 2003-05-30 | 2005-12-27 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
DE102006006570A1 (de) * | 2006-01-31 | 2007-08-09 | Infineon Technologies Ag | Verfahren zur Herstellung von Anordnung von Leitern auf Halbleiterbauelementen |
DE102007008934A1 (de) * | 2007-01-29 | 2008-08-28 | Qimonda Ag | Vorrichtung und Speichervorrichtung, Verfahren zur Herstellung von Strukturen in einem Werkstück und Verfahren zur Herstellung einer Speichervorrichtung |
-
1980
- 1980-03-28 JP JP4089980A patent/JPS56137632A/ja active Granted
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6010624A (ja) * | 1983-06-29 | 1985-01-19 | Mitsubishi Electric Corp | パタ−ン形成方法 |
US5981114A (en) * | 1993-11-16 | 1999-11-09 | Nec Corporation | Photoresist check patterns in highly integrated circuits having multi-level interconnect layers |
US6979860B2 (en) * | 2003-05-30 | 2005-12-27 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US7241651B2 (en) | 2003-05-30 | 2007-07-10 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method |
US7422937B2 (en) | 2003-05-30 | 2008-09-09 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US7544613B2 (en) | 2003-05-30 | 2009-06-09 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device with an improved wiring layer structure |
DE102006006570A1 (de) * | 2006-01-31 | 2007-08-09 | Infineon Technologies Ag | Verfahren zur Herstellung von Anordnung von Leitern auf Halbleiterbauelementen |
DE102007008934A1 (de) * | 2007-01-29 | 2008-08-28 | Qimonda Ag | Vorrichtung und Speichervorrichtung, Verfahren zur Herstellung von Strukturen in einem Werkstück und Verfahren zur Herstellung einer Speichervorrichtung |
Also Published As
Publication number | Publication date |
---|---|
JPS6310891B2 (enrdf_load_stackoverflow) | 1988-03-10 |
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