JPS56130974A - Insulated gate type semiconductor device - Google Patents

Insulated gate type semiconductor device

Info

Publication number
JPS56130974A
JPS56130974A JP3381280A JP3381280A JPS56130974A JP S56130974 A JPS56130974 A JP S56130974A JP 3381280 A JP3381280 A JP 3381280A JP 3381280 A JP3381280 A JP 3381280A JP S56130974 A JPS56130974 A JP S56130974A
Authority
JP
Japan
Prior art keywords
drain
source
substrate
region
depletion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3381280A
Other languages
Japanese (ja)
Inventor
Hideyoshi Shimura
Takashi Osone
Hirohei Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3381280A priority Critical patent/JPS56130974A/en
Publication of JPS56130974A publication Critical patent/JPS56130974A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To suppress the bias effect of the substrate of an MOSFET by specifying the shape of an insular region and thus preventing the infinitesimal punch- through current flowing from a drain to a semiconductor substrate. CONSTITUTION:A reverse conductivity type insular region 32 is formed on a semiconductor substrate 34, and a gate 31 is formed via an insulating film 30 between the source 28 and the drain 29 on the surface of a substrate 34 to form the source 34 and the drain 29 on the region 32. When a voltage between the source 28 and the semiconductor substrate 34 or the insular region 32 is increased by calculating and setting the expansion of a depletion layer under the source and the drain under the conditions of forming an MOS semiconductor in a depth of the insular region under the source 28 and the drain 29, the depletion layer under the source 28 is connected to the substrate 34, but the depletion layer under the drain 29 can be disconnected from the substrate 34.
JP3381280A 1980-03-17 1980-03-17 Insulated gate type semiconductor device Pending JPS56130974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3381280A JPS56130974A (en) 1980-03-17 1980-03-17 Insulated gate type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3381280A JPS56130974A (en) 1980-03-17 1980-03-17 Insulated gate type semiconductor device

Publications (1)

Publication Number Publication Date
JPS56130974A true JPS56130974A (en) 1981-10-14

Family

ID=12396884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3381280A Pending JPS56130974A (en) 1980-03-17 1980-03-17 Insulated gate type semiconductor device

Country Status (1)

Country Link
JP (1) JPS56130974A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788170A2 (en) * 1996-02-05 1997-08-06 EASTMAN KODAK COMPANY (a New Jersey corporation) Source-follower amplifier employing a fully depleted well structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788170A2 (en) * 1996-02-05 1997-08-06 EASTMAN KODAK COMPANY (a New Jersey corporation) Source-follower amplifier employing a fully depleted well structure
EP0788170A3 (en) * 1996-02-05 1997-12-10 EASTMAN KODAK COMPANY (a New Jersey corporation) Source-follower amplifier employing a fully depleted well structure

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