JPS56127247A - Operation controller - Google Patents

Operation controller

Info

Publication number
JPS56127247A
JPS56127247A JP3053180A JP3053180A JPS56127247A JP S56127247 A JPS56127247 A JP S56127247A JP 3053180 A JP3053180 A JP 3053180A JP 3053180 A JP3053180 A JP 3053180A JP S56127247 A JPS56127247 A JP S56127247A
Authority
JP
Japan
Prior art keywords
address
stop
testt1
cpu101
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3053180A
Other languages
Japanese (ja)
Inventor
Tsuneo Kinoshita
Fumitaka Sato
Isamu Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3053180A priority Critical patent/JPS56127247A/en
Priority to DE8181101194T priority patent/DE3176840D1/en
Priority to EP81101194A priority patent/EP0036093B1/en
Priority to DE8484105306T priority patent/DE3177096D1/en
Priority to EP84105306A priority patent/EP0139080B1/en
Priority to US06/236,116 priority patent/US4616331A/en
Publication of JPS56127247A publication Critical patent/JPS56127247A/en
Priority to US06/886,807 priority patent/US4734849A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Advance Control (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To always secure an address stop in a correct timing for an operation controller including an instruction prefetching buffer formed into a chip, by deciding the presence or absence of the address stop in case an instruction is read out of the instruction prefetching buffer. CONSTITUTION:A comparison is given between the memory address to which an application of address stop is desired and the memory address that is used when the 1-chip CPU101 gives an access to the main memory through the address matching mechanism 300 provided outside. When a coincidence is obtained, the AM signal of a bit is delivered to TESTT1. In the normal microprogram leading mode, the external signal group of TESTT1 is taken into the CPU101 along with a microinstruction by the opening of the gate G3. Thus an address stop is always possible in a correct timing by the AM signal.
JP3053180A 1980-02-25 1980-03-11 Operation controller Pending JPS56127247A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP3053180A JPS56127247A (en) 1980-03-11 1980-03-11 Operation controller
DE8181101194T DE3176840D1 (en) 1980-02-25 1981-02-19 An information-processing system consisting of an arithmetic control unit into a one-chip type by application of a highly-integrated semiconductor device
EP81101194A EP0036093B1 (en) 1980-02-25 1981-02-19 An information-processing system consisting of an arithmetic control unit into a one-chip type by application of a highly-integrated semiconductor device
DE8484105306T DE3177096D1 (en) 1980-02-25 1981-02-19 An information-processing system
EP84105306A EP0139080B1 (en) 1980-02-25 1981-02-19 An information-processing system
US06/236,116 US4616331A (en) 1980-02-25 1981-02-19 Information processing system consisting of an arithmetic control unit formed into a one-chip typed by application of a highly-integrated semiconductor device
US06/886,807 US4734849A (en) 1980-02-25 1986-07-16 Information-processing system having a single chip arithmetic control unit with means for prefetching instructions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3053180A JPS56127247A (en) 1980-03-11 1980-03-11 Operation controller

Publications (1)

Publication Number Publication Date
JPS56127247A true JPS56127247A (en) 1981-10-05

Family

ID=12306374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3053180A Pending JPS56127247A (en) 1980-02-25 1980-03-11 Operation controller

Country Status (1)

Country Link
JP (1) JPS56127247A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197546A (en) * 1982-05-13 1983-11-17 Mitsubishi Electric Corp Compensating device for instruction queue
JPS59125449A (en) * 1982-12-31 1984-07-19 Fujitsu Ltd Control system of virtual computer
JPS619734A (en) * 1984-06-26 1986-01-17 Nec Corp Processor control system
JPH0399338A (en) * 1989-09-12 1991-04-24 Fujitsu Ltd Microprocessor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197546A (en) * 1982-05-13 1983-11-17 Mitsubishi Electric Corp Compensating device for instruction queue
JPS6232509B2 (en) * 1982-05-13 1987-07-15 Mitsubishi Electric Corp
JPS59125449A (en) * 1982-12-31 1984-07-19 Fujitsu Ltd Control system of virtual computer
JPS619734A (en) * 1984-06-26 1986-01-17 Nec Corp Processor control system
JPH0332818B2 (en) * 1984-06-26 1991-05-14 Nippon Electric Co
JPH0399338A (en) * 1989-09-12 1991-04-24 Fujitsu Ltd Microprocessor

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