JPS58197546A - Compensating device for instruction queue - Google Patents

Abstract

PURPOSE:To compensate the time lag between fetch and execution of an instruction queue, by connecting the control bus of a microprocessor with a status converting circuit, and connecting a circuit for storing addresses from the microprocessor to an address bus. CONSTITUTION:A data bus 2, address bus 3, and control signal bus 4 are connected to the microprocessor MPR1, and the status converting circuit to the control signal bus 4. A first-in.first-out (FIFO) memory 12 to be controlled is connected to the status converting circuit 9. The FIFO memory 12 is stored with the address at the point of instruction fetch and the address is outputted at its execution point. A comparator 8' is connected to an execution address bus 13 to make a comparison with the address that a latch circuit 7 latches. Consequently, the difference of address between the fetch point and execution point is compensated easily.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to, for example, a microprocessor having an internal instruction queue, and relates to an instruction queue compensation device that compensates for the difference between the timing of fetching an instruction from a main memory and the timing of executing that instruction. It is.

Figure 1 shows a conventional device of this type, with main memory I! FIG. 2 is a block diagram illustrating a case of detecting the execution point of an instruction stored at a designated address of a location; In the figure, (
1) is a microprocessor, (2;, (3), and (4
) are a data bus, an address bus, and a control signal bus connected to the data input terminal, address output terminal, and control output terminal of the microprocessor (1), respectively, and these data buses (2) address Bus (3) and system? The main memory W 16゛f51 and the input/output 11 are connected to the microprocessor (1) via the m'tp bus (4).
1 (6) is connected. (7) is the address bus (3
), (8) is a comparator that compares the output of this latch circuit (7) with the address output by microprocessor (1), and (9) is a control signal bus. (4) to monitor the status of the microprocessor (1), and when an instruction is fetched, the counter (1
When the countdown signal Sa't, -fta1111 moves to the location, the counter screams, and the α crocodile reset signal S
The counter 011 has a preset data input terminal connected to the count output terminal of the counter flO, and a preset input terminal connected to the minus number output terminal of the comparator (8). .

In the above configuration, the microprocessor (1) normally executes a program while repeating the steps shown below.

Step 1. Main memory! #(Reads the next instruction to be executed from 51 (called L-1 lower instruction fetch).

Step 2. If necessary, read the operand from main memory (5).

Step 3. Execute commands.

Step 4. If necessary, the main memory device I (51 or the output device 77 device (6)) is saved.

Here, the microprocessor (1) is inside! It has an 11sK instruction queue, and steps 1 and 3 above can be performed in parallel. That is, while an instruction is being executed, several instructions to be executed below can be prefetched, and therefore,
For such a microprocessor (1), it is necessary to compensate for the difference between the fetch timing and the execution timing, and the compensation tf[ having the configuration shown in FIG. 1 operates as follows.

That is, the microprocessor (1) outputs a status indicating the execution of the above-mentioned step, and the status conversion circuit (9) outputs a status indicating the execution of the above-mentioned step. )?
I,, When the start information of step 1 is obtained, that is, when the cold 7th
1 and obtains the start information τ of step 3, the processor (1) executes program control such as a jump instruction.
When the instruction to move to the location ll is executed, the instructions fetched up to that point will become invalid and the instruction queue will be flushed without being executed.When the status conversion circuit (9) obtains this information, Counter Q (j and 0]
) The count value of the counter (IO) which outputs the heliset signal Sr means the number of instructions currently stored in the instruction queue.

By the way, if the memory address of the instruction whose execution time is to be known is stored in advance in the latch circuit (7) and the program is executed, the comparator (8) makes several output signals Sa significant at the time when the instruction is fetched. Counter (1
A count value of 0 is set in the counter Ql). That is, the number of instructions stored in the instruction queue at the time of fetch is input to the counter qυ, and the counter qυ is counted down each time an instruction is executed thereafter. Also, if the instruction queue is flushed during the countdown, it becomes invalid, and by doing so, the time when the count value of the counter 0υ becomes 0 is the same as the time when the instruction is executed.

Conventional instruction queue compensation devices are configured as shown above, so if you want to detect the customary points of multiple instructions, you must prepare the same number of compensation devices. Cue compensator.

For example, J? Memorize the executed instructions in the order of execution 5
- A shortcoming in such a trace storage device is that it is difficult to compensate for the instruction queue.

Therefore, the present invention has been made in order to eliminate the deficiencies of the conventional methods as described above, and is a trace memory that can detect bold line ending points of multiple instructions and stores executed instructions according to the order of execution. The purpose of the present invention is to provide a compensating device for a snowy instruction queue that is simpler to apply to a device.

An embodiment of the present invention will be described with reference to FIG. 2, which shows its application to a circuit for detecting the execution time of an instruction. In FIG. 2, the same reference numerals as in FIG. 1 are omitted, and α4 is controlled by a status conversion circuit (9), which inputs and stores the address at the time of fetch from the address bus (3), and stores it at the time of execution. Outputs the address to the execution address bus (+3) '1rst InFirstOut memory (Kagashita F
The comparator (8) is connected to this execution address bus (1) and is connected to the latch circuit (7).
) and the address stored in (>).Others are conventional and Inl-like.

6- In the configuration shown in FIG. 2, when the status conversion circuit (9) obtains the start information of step 1, that is, when fetching an instruction, it outputs a Write clock to the FIFO memory α2, and this Write clock causes the FIFO
The FO memory ^) stores the address at the time of fetch.

When the status conversion circuit (9) obtains the start information of step (3), that is, when executing the instruction, it outputs the R8ad clock to the FIFO memory (1), and as a result, the FIFO memory α2 is input. 111
K[WR6ad clock will output the storage address. This output address is the address of the main memory #f51 where the instruction currently being executed by the microprocessor (1) was stored. If further instruction queues flow, the status conversion circuit (9)
Since the FO memory +12 is reset, the address information input up to that point becomes invalid and will not be output. Here, if the memory capacity t of the FIFO memory 04 is larger than the capacity of the instruction queue of the microprocessor (1), then by the operation described above, the execution address bus (13) is always Therefore, when the address of the instruction to be detected is stored in the latch circuit (7) in advance and the program is executed, the address of the instruction to be detected will be output.
) will output the Isshitoshi detection signal at the time of execution.

In the above embodiment, the detection of the execution point of one instruction has been described, but it goes without saying that the execution @point detection of a plurality of instructions is possible. Furthermore, by connecting a storage device or the like to execution address 03, it is of course possible to easily configure a trace storage device that compensates for the instruction queue.

As mentioned above, according to the present invention, it is easy to compensate for the difference between the fetch time and the execution time for a microprocessor having an internal instruction queue, and it is also easy to apply to a trace storage device. 9. Compensation device for instruction queue is paid.
It will be done.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional instruction queue compensation device, and Figure 2 is a block diagram showing an embodiment of the present invention. (1): Microprocessor, I'll: Datano (
(3) Two-way address bus, (4) Two-side signal node, (5): The above-mentioned system, (6) Two-person output device f, (7): Latch circuit, ( 8), (8)
:Conno(rate),(9):Status conversion circuit,(1
0, α1): Counter. (1', U: FIFO memory, Oj: Execution address nox. In the figures, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - 9- Figure 1 Figure 2 432 13 Procedures Correction a (spontaneous) T1 + i'l'I' + Chomiya 1, Display of 11 items f, y Gansho 57-8187
No. 7 2. Name of the invention Instruction queue compensation device; 3. Ura 11:, 4-R Relationship with the case Patent applicant address Higashijo;
'l12-38'' Name (601): Ryodenki Co., Ltd. Representative Yuhito Daikata 8be 1, agent work: Higashi 3ij Tochodai 11 (Marunouchi-J, Ward)
-1'+2 No. 35;・5 car stop object light na gong's %Fr s-h aspect of the bell 1 surrounding, and,
Aspects of the Detailed Description of the Invention. 6. Contents of the cuffs (1) The description of Patent H, request for consideration, and permission in Specification 1 will be amended as indicated separately. (2) At the time of location transfer, the entry “-1” on the first collar of the statement clerk 2's car 20 Jinokino 3's location was changed to ``Oka who issued the order to move to the location of the 10 gram system/monk meeting. ” I corrected myself. (Kohe・Details W 5th member and a half 12 attachment to drive 13← ``If it is washed away, it becomes invalid, and the 6 self M of 1 becomes ``When it is washed away, the count value k Sl! + of counter αII becomes effective. J and f Stop the car. 7. Zazuke - Chi's 1st ball + li eye hit special, * aW/Ko's order is listed on the 11th mountain top 2 - Supplementary 9th mark total seizoku's 1 ) The written daily schedule that describes the order has been submitted to the microprocessor that can be used to carry out the order and execute the order. The main storage device and the turnout 7'I device 1, the upper i4a system button number bus are nervous and the micro 70 person's Q status is recovered, wholesale] a
]S-tanu-hai outputting the ir-number [l-l1 road,
The memory used to write the address output from the microprocessor (after +i + % is l, the Soehaku device a0 of Reihani)

Claims (1)

[Claims] Has an internal instruction queue for instruction execution and instruction control signal bus,
Main memory connected via address bus and data path! 2 acids, and input and output i! Acid, above? 1llll@l Status f conversion circuit that is connected to the signal bus and monitors the status of the microprocessor and outputs the signal 1 when converting the status, and the signal 111i11 (2) is used to convert the signal 1 and output it from the microprocessor. An instruction queue compensating device specially equipped with a memory that stores addresses in accordance with the instruction execution order.