JPH0477933A - Microprocessor for evaluation - Google Patents

Abstract

PURPOSE:To measure the coverage of an instruction which does not include invalid fetch and which is actually executed by connecting the value of a pro gram counter holding the address value of the instruction which is to be execut ed next and an instruction fetch signal showing the executing timing of the executed instruction to a coverage measurement circuit. CONSTITUTION:A control circuit 5 outputting the value of the program counter 6, which exists in an execution unit 2 in a microprocessor which holds the execution address of the next instruction, and the instruction fetch signal from an instruction queue buffer 3 in the microprocessor to the execution unit 2 to the coverage measurement circuit is provided. The value of the program counter 6 at the time of the output timing of a negative logic instruction fetch signal (QRD signal) 7 for one system clock shows the address value of the instruction which the microprocessor for evaluation 1 actually executes. Thus, the coverage measurement of the program which does not include invalid fetch and which is actually executed can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an evaluation microprocessor used in an in-circuit emulator, and more particularly to an evaluation microprocessor having an instruction prefetch function.

[Conventional technology]

In general, in-circuit emulators are widely used as hardware and software debugging devices when developing applied devices using microprocessors.

An in-circuit emulator uses an evaluation microprocessor that performs operations equivalent to the target microprocessor to execute and stop programs in place of the microprocessor in the target microprocessor application device, and to reference memory contents. It has functions such as changing, referencing and modifying register contents.

In recent years, in this type of in-circuit emulator,
The number of tools that can measure program coverage is increasing. Coverage is the coverage of all instructions in a program.
It is an index that shows what percentage of the entire program has instructions that have been executed at least once, and is one of the criteria for measuring the degree of achievement of the program's test. The general method for performing the above coverage with an in-circuit emulator is to have a coverage measurement memory that corresponds one-to-one with the program memory, and when a program is fetched, write information that the program has been fetched to the coverage measurement memory. It is.

The above-mentioned conventional technology will be explained using the drawings. FIG. 5 is a diagram showing a coverage measurement circuit of an in-circuit emulator. Evaluation microprocessor (C) 3
0 functions equivalent to the microprocessor installed in the target microprocessor application equipment. A supervisor (CPU) 31 controls the entire in-circuit emulator. Evaluation microprocessor 3
0 and supervisor 31 are stored in buffer 33.0 and supervisor 31, respectively. It is connected through a buffer 34 to an address input (A) of a coverage measurement memory 35. Program fetch signal (FE) of the evaluation microprocessor 30
TCH) 39 and supervisor 31 write signal (WR)
40 is the coverage measurement memory 3 through the selector 36.
5 WR large input, supervisor 3] read signal (RD
)'41 is connected to the output enable (OE) of the coverage measurement memory through the selector 36, and the data bus is connected to the data input/output (D) through the bidirectional buffer 38.
It is connected to the.

Next, the operation of this coverage measurement circuit will be explained.

When the program of the evaluation microprocessor 30 or the target microprocessor application device is not running (in the break state), the BREAK/RUN signal 3
2 becomes "1". At this time, the buffer 33 and the buffer 37 are in a high impedance state, the buffer 34 and the bidirectional buffer 38 are in an active state, and the selector 36 is in an I state.
B, 2B input is selected. That is, in the break state, all signals of the supervisor 31 are connected to the coverage measurement memory 35, and in this state, all "0's" are written in the coverage measurement memory 35 in advance.

Next, when the evaluation microprocessor 30 starts executing the program of the target microprocessor application device (run state), the BREAK/RUN signal 32 becomes 0°, and the buffer 34 and bidirectional buffer 38 become high impedance. Further, the buffers 33 and 37 are in the active state, and the selector 36 selects the LA and 2A inputs. In other words, in the run state, the address output of the evaluation microprocessor 30 is
Program fetch signal (FET
Since CH) 39 is connected to write (WR), 1' is written to the coverage measurement memory 35 at the same address as the address where the program was fetched.

Therefore, after the evaluation microprocessor 30 stops executing the target program, the supervisor 31 reads the contents of the coverage measurement memory 35 in the break state, thereby making it possible to determine which parts of the program have been fetched and which parts have not been fetched. .

[Problem to be solved by the invention]

The coverage measurement circuit of the conventional in-circuit emulator described above is a circuit that measures the target program fetch operation of the evaluation microprocessor.

Therefore, a microprocessor with an instruction prefetch function (
The evaluation microprocessor also measures invalid fetch operations that are pre-fetched into the instruction queue and then invalidated without being executed due to the execution of a branch instruction. For this reason, as described in the prior art, when measuring coverage to determine what percentage of the total program the executed program corresponds to, if the program uses many branch instructions and the number of buffer stages in the instruction queue buffer is large,
There is a drawback that an error of about 20% occurs.

[Means to solve the problem]

In an evaluation microprocessor used in an in-circuit emulator of a microprocessor having an instruction prefetch function, the present invention relates to the value of a program counter existing in an execution unit within the microprocessor that holds the execution address of the next instruction, and the instruction queue within the microprocessor. The control circuit includes a control circuit that outputs an instruction fetch signal from the buffer to the execution unit to the outside.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Referring to FIG. 1, which shows a first embodiment of the present invention, there is shown a general internal hardware configuration of an evaluation microprocessor <A) 1 having an instruction prefetch function. The bus control unit 4 fetches the instruction code in advance,
This is an interface unit with an external storage device that generates bus cycles such as data access. The instruction queue buffer 3 is a FIFO memory that temporarily holds instructions fetched in advance by the bus control unit 4. The execution unit 2 takes in the instructions held in the instruction queue buffer 3 and actually processes them. The execution unit 2 mainly includes a micro ROM that stores microcode that describes operations for each instruction, a microsequencer that decodes instructions and executes the microcode, and a program that always holds the execution address of the next instruction. counter 6
It is made up of. The control circuit (A) 5 is composed of an output buffer 14, a program counter output terminal 11, and a QRD signal output terminal 12. Command capture signal 7
(QRD signal) is a negative logic signal of one system clock indicating the timing of fetching an instruction from the instruction queue buffer 3 to the execution unit 2. Command write signal 8 (QW
R signal) indicates the timing at which the instruction previously fetched by the bus control unit 4 is written to the instruction queue buffer 3.
This is the negative logic signal of the system clock. Instruction queue stop signal 9 (QSTP signal) is sent to instruction queue buffer 3
This is a negative logic timing signal indicating that the The instruction queue flush signal 1° (QFL signal) is a negative logic signal of one system clock indicating the timing to invalidate (flush) instructions held in the instruction queue buffer 3 that are no longer needed due to execution of a branch instruction.

Next, the operation timing of each signal mentioned above and the value of the program counter 6 will be explained with reference to the operation timing chart of each signal line shown in FIG. In order to specifically explain the relationship between invalid fetch operations, the program counter 6, and the QRD signal 7, FIG. branch instruction (the storage address of the branch instruction is N, N+
1, N+2> is fetched in advance and is actually executed. The program counter 6 initially indicates the start address N of the next instruction to be executed (branch instruction in this case). In this state, the bus control unit 4 generates advance fetch bus cycles ①, ②, ② consisting of three system clocks since the bus is not exclusively used for processing the previous instruction. On the other hand, the instructions fetched in advance by the bus control unit 4 by the bus cycles ■, ■, ■ are the QWR signals 8, ■′.

The commands are written to the instruction queue buffer 3 one after another at the timings ■' and ■'. At this time, by writing ■', the instruction queue buffer 3 becomes full, and the QSTP signal 9 (■) is output, and the next preceding fetch bus cycle (■) is interrupted.

At the same time, the processing of the previous instruction is completed at this timing, and the next instruction is executed, so the QRD signal 7 is
" becomes active, and branch instructions (N), (N+1>, (N+2>) are transferred from the instruction queue buffer 3 to the execution unit 2.
be taken into. On the other hand, the QSTP signal 9 ■ becomes inactive because the instruction queue buffer 3 becomes empty again due to the fetching of the instruction into the execution unit 2, and the preceding fetch bus cycle ■ continues again, and the instruction queue is queued at the timing of ■'. Instructions are written to the buffer one after another. The value of the program counter 6 is the capture timing of the instruction capture signal 7 to the execution unit 2.
■N+1 according to “”. N+2. It is incremented as N-1-3. Next, by executing the branch instruction taken into the execution unit 2, the branch destination address K is set in the program counter 6, and at the same time, the instruction queue buffer 3 is set.
■ of QFL signal 10 indicating the flash operation timing of
and outputs the preceding fetch bus cycle■, that is, QWR
The instruction written to the instruction queue buffer 3 by signal 8 (
N-1-3) is invalidated, and the branch instruction execution process ends. The bus control units 1 to 4 generate a preceding fetch bus cycle (■) from the branch destination address K in accordance with the execution processing of the branch instruction, and from then on until the next branch instruction is executed again, +1. +2. +2... and the advance fetch operation continues.

As explained above, the value of the program counter 6 at the output timing of the negative logic instruction capture signal (QRD signal) 7 of one system clock indicates the address value of the instruction actually executed by the evaluation microprocessor 1. The value of the program counter 6 and the QRD signal 7 are sent to the buffer 14, the program counter output terminal 11. A control circuit 5 configured with a QRD signal output terminal 12 outputs the signal to the outside.

Next, referring to FIG. 3 showing the internal hardware configuration of the evaluation microprocessor (B) 20 according to the second embodiment of the present invention, this microprocessor 20 includes an execution unit 2, an instruction queue buffer 3, a bus The control unit 4 and the blocks are all the same as the evaluation microprocessor (A) 1 of the first embodiment, so the explanation will be omitted. The control circuit (B) 21 includes a selector 22, an output buffer 14 and a QR
It is composed of a D signal output terminal 12.

In this embodiment, as a method for deriving the value of the program counter 6 to the outside, the existing address bus output terminal 15 is used instead of providing a dedicated program counter output terminal 11 as in the second embodiment. . As a result, the number of terminals of the evaluation microprocessor 20 can be reduced by about 16 to 24 compared to the microprocessor 1.
The cost of the packages used can be reduced.

Next, the operation of the address bus output terminal 15 mentioned above will be explained with reference to FIGS. 3 and 4. The address bus 13 outputted from the bus control unit 4 and the program counter output bus 23 outputted from the program counter 6 are connected to the terminals B and A inputs of the selector 22, and the output is passed through an output buffer to the address bus output terminal 15. It is connected to the. The QRD signal 7 is connected to the WAIT input of the bus control unit 4 and the selector 2 of the selector 22.
It is connected to the selector S of No. 2, and is also connected to the QRD signal output terminal 12 through the output buffer 14. When QRD signal 7 is inactive (positive logic)
, the B input of the selector 22 is selected, and the address bus 13
is connected to the address bus output terminal 15. Also, QR
When the D signal switch becomes active (negative logic), WAIT of the bus control unit 4 becomes valid and interrupts the currently generated bus cycle. On the other hand, the A input of the selector 22 is selected, the program counter output bus 23 is connected to the address bus output terminal 15, and the value of the program counter 6 is output.

When QRD signal 7 becomes inactive again, WA
IT is disabled, the interrupted bus cycle is resumed, and selector 22 is switched to address bus 1.
3 is connected to the address bus output terminal 15. FIG. 4 explains the timing of the above-mentioned operation using the operation sequence (pre-fetch, branch instruction execution) explained in the first embodiment. N, N+1 . N+2
is output to the address bus output terminal 15.

The WAIT input of the QRD signal 7 becomes valid at the timing ◎, and the preceding fetch bus cycle ■ is temporarily suspended. In this case, since the interruption time is as long as 3 system clocks, the branch instruction execution processing in the execution unit 2 is completed before the invalid fetch bus cycle (2) is completed, and the next branch destination is output with the output of the QFL signal 10. A prefetch bus cycle is generated for the address.

〔Effect of the invention〕

As explained above, the value of the program counter that holds the address value of the next instruction to be executed outputted by the evaluation microprocessor of the present invention, and the instruction capture signal (Q R, D By connecting the coverage measurement memory address input and WR large input of the coverage measurement circuit shown in the prior art to the coverage measurement circuit shown in the prior art, coverage measurement of only actually executed instructions without including invalid fetches can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the internal hardware configuration of the evaluation microprocessor according to the first embodiment of the present invention, FIG. 2 is an operation timing diagram of the microprocessor shown in FIG. 1, and FIG. FIG. 4 is an operation timing diagram of the microprocessor shown in FIG. 3, and FIG. 5 is a diagram showing a coverage measurement circuit of a conventional in-circuit emulator. It is.

Claims (1)

[Claims] In an evaluation microprocessor used in an in-circuit emulator of a microprocessor having an instruction prefetch function, the program counter value existing in the execution unit in the microprocessor that holds the execution address of the next instruction and the above value from the instruction queue buffer in the microprocessor are used. An evaluation microprocessor characterized by comprising a control circuit that outputs an instruction capture signal to an execution unit to the outside.