JPH02162435A - Microprocessor and in-circuit emulator - Google Patents

Abstract

PURPOSE:To accurately decide the final machine cycle of the final instruction of a user program as well as a break point by outputting a DEC signal to show whether the instruction fetched by an instruction address outputted by a target CPU in a machine cycle preceding by one cycle should be decoded in the present machine cycle or not. CONSTITUTION:A microprocessor (target CPU) 9 outputs a DEC signal to show whether an instruction address is valid or not. A breakpoint detecting circuit 8 compares the instruction address with a breakpoint address and then checks the DEC signal when the coincidence is obtained between both addresses to decide the presence or absence of a breakpoint. A user program end detecting circuit 5 continues the monitor of the DEC signal after the change of a non- maskable interruption NMI signal and decides the end timing of a user program. Thus it is possible to detect a breakpoint and to accurately detect the final cycle of the final instruction of the user program.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an in-circuit emulator for switching between execution of a user program and execution of a monitor program, and a microprocessor used in the in-circuit emulator. .

[Conventional technology]

Conventionally, as this type of in-circuit emulator, there has been one as shown in Takashi Maruyama's "Introduction to In-Circuit Emulator" Interface, September 1982, Nα64PP138-14F.

Figure 2 is a configuration diagram of such a conventional in-circuit emulator system. In Figure 1, 111 is the target CPLIA that the in-circuit emulator is debugging, and 12+ is the target CPLIA (Targuera) CPUA III.
monitors the instruction address output by

A breakpoint detection circuit detects the execution of the instruction at the address where a breakpoint has been set, (3) is the instruction address output by the target CPU AIII, and (4) is a breakpoint detection circuit (2) that detects the execution of the instruction at the target CPUAl1.
This is an NMI (non-maskable interrupt) signal for notifying the detection of a breakpoint.

Next, the operation will be explained. In a system having such a configuration, the transition from the user program to the monitor program upon detection of a breakpoint is performed as follows by operating the system of FIG. 2 at the timing shown in the timing chart of FIG. 3.

First, address N is set as a breakpoint in the breakpoint detection circuit (2) in advance. When the user program is executed on the target CPU A 111 in this state, the instruction address (3) is set as the target CPU
The breakpoint detection circuit (2) compares this value with a preset address N every machine cycle. When the address N is output as the instruction address (3) in the second machine cycle in Fig. 3, the breakpoint detection circuit (2) detects the breakpoint at the end of the second machine cycle after a certain period of time necessary for detection has elapsed. NM! Change the signal +a Miralobel to high level. NM+ signal (4) while executing the instruction at address N
In response to this, the target CPU An+ executes an interrupt processing operation after completing execution of this instruction, and transfers control to a predetermined address (address 1 in the case of this CPU). Since the monitor program was stored in advance at address 1 and after, it was possible to stop the execution of the user program at breakpoint N and immediately start executing the monitor program in steps 9 and above.

In addition, in this conventional system, all instructions complete in one machine cycle, so the breakpoint address N
The machine cycle in which is detected is the first machine cycle of the last instruction of the user program, and is also the last machine cycle.

[Problem to be solved by the invention]

The conventional in-circuit emulator control device is configured as described above, and it is assumed that when the target CPU outputs a certain instruction address, the instruction at that address is always executed.

It was assumed that all instructions complete execution in one machine cycle. On the other hand, the target CPU 19+ that this invention assumes operates in a three-stage pipeline of fetch, decode, and execution, so the instruction address output in a fetch cycle is invalidated in the next decode cycle. Sometimes. Therefore, if a breakpoint instruction that is not actually executed is executed, it may be mistakenly determined and the program will stop.

・Basically, it operates in a three-stage pipeline.

Depending on the instruction, an execution cycle of one machine cycle, two machine cycles, or even more execution cycles may be added.

(In that case, a NOP cycle is inserted into the decode cycle.) Therefore, it is not known from outside the CPU where the last machine cycle of the last instruction of the user program is.

Due to these problems, the conventional method has had the problem that it is not possible to accurately detect a breakpoint or the last machine cycle of the last instruction of a user program.

This invention was made in order to solve the above-mentioned problems, and it is possible to accurately determine the breakpoint and the last machine cycle of the last instruction of the user program for the target CPU 191 as described above. purpose.

[Means for Solving the Problems] The microprocessor according to the present invention is a microprocessor that performs pipeline operation, i.e., a Targetera CPUUS,
It has a function of outputting from the target CPUB a DEC signal indicating whether or not the instruction fetched based on the instruction address output in the last machine cycle is to be decoded in the current machine cycle. An in-circuit emulator according to another invention has a function of determining whether or not an instruction address output in one mf machine cycle is recognized as a breakpoint by the DEC signal. An in-circuit emulator according to another aspect of the invention has a function of determining the last machine cycle of the last instruction to be executed in a user program based on the DEC signal.

[For production]

The microprocessor (target CP) in this invention
UB) outputs a DEC signal indicating whether the instruction address is valid or not.

Breakpoint detection circuit B compares the instruction address and breakpoint address, and if they match, further DE
Check the C signal and determine whether it is a breakpoint.

The user program end detection circuit detects a change in the NMI signal i&
Continue monitoring the DEc signal to determine the end timing of the user program.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (9; means 7 etches and decodes.

Target CPL that operates on a three-stage pipeline of execution
JB, [31 is the instruction address output by the target CP IJ B +9+, (5) is the user program end detection circuit that determines the last machine cycle of the last instruction to be executed in the user program, and (6) is the target CP
A DEC signal (7) output by the target CPU B +9+ to indicate whether or not the instruction fetched by the instruction address (3) output by the LJ B 191 in one machine cycle is to be decoded in the current machine cycle. is the signal output by the user program end detection circuit (5) to indicate the end timing of the knee program, and (8) is the instruction address output by the target CPU B+91 (31 and the breakpoint address previously set in the internal register). The breakpoint detection circuit B, t41, has the function of comparing the DEC signal (6) and determining whether or not the instruction at the address where the breakpoint has been set has been executed. 8) outputs the target CPU U B +
NMI to notify 9+ of breakpoint detection
(non-maskable interrupt) signal.

Next, the operation will be explained.

First, D to be output to the target CPU B +91
EC (f No. +61 will be explained. This signal changes immediately after the start of every machine cycle, and in one machine cycle, the instruction fetched by the instruction address (3) output by the target CPU B +91 is transferred to the current machine cycle. This is a signal indicating whether or not decoding is to be performed in the target CPU B+9+, and is generated from the decoder control signal inside the target CPU B+9+.

The function of this signal is further explained in FIG. 4, which is a timing chart showing the pipeline operation of target CPU B 191. In FIG. 4, the instruction fetched by N-1 of the instruction address (3) output by the target CP LJ B +9+ in the first machine cycle is decoded in the second machine cycle.

This is a valid instruction executed in the third machine cycle. To indicate this validity, the DEC signal (6) is brought to a high level in the second machine cycle, ie, the decode cycle of the instruction fetched by address N-1. Next 2
Instruction address output in the th machine cycle (3)
Since it is known at the end of the second machine cycle that the instruction fetched by N is an invalid instruction because it branches to address X due to the establishment of the branch instruction at address N-1, this instruction is executed in the third machine cycle. is not decoded. To indicate this invalidity, the EC signal (6) is brought to a low level in the third machine cycle, that is, the decode cycle of the instruction fetched by address N. For the same reason, the DEC signal goes high in the fourth and fifth machine cycles.

Next, the operation of the breakpoint detection circuit B (8) detecting a breakpoint using the DEC signal (6) will be explained with reference to FIGS. 4 and 5. First, execution of the user program is started with a breakpoint address set in the breakpoint detection circuit B (8) in advance. Breakpoint detection circuit B (8) during user program execution
) compares the instruction address (3) and the breakpoint address every machine cycle, and if they match, there is a possibility of a breakpoint, so o is omitted in the first machine cycle.
Ecft number ts+ is checked to see if this instruction address (3) is valid. Here, if the DEC signal is at a high level as in the case of the third machine cycle in Figure 5, the instruction address (3) is valid and the instruction at the breakpoint address will actually be decoded and executed. Breakpoint detection circuit B +8
11; i N M l +41t-changes from low level to high level to issue a non-maskable interrupt to the target CPU 191 and command to stop the user program and start the monitor program. FIG. 5 shows the overall breakpoint detection time and decode signal check time in this case. Also, as in the case of the third machine cycle in Figure 4, if the DEC signal (6) is at a low level at the checkpoint shown in the figure, then the instruction found by temporary breakpoint detection in the figure to match the breakpoint address. The instruction fetched by address (3) becomes invalid and is not decoded, so N M l 141 is not changed.

Finally, a method for the user program end detection circuit (5) to detect the last machine cycle of the last instruction of the user program using the NMI (4) and DEC signal (6) will be explained.

In the example shown in Fig. 5, a breakpoint is set at instruction address N, and after the execution of the instruction at address N is completed, a non-maskable interrupt is used to transition to the monitor program from address 1, but this instruction at address N takes two machine cycles. This is an instruction to which an extra actual cycle is added, and the end of execution of the instruction is delayed by that amount. Furthermore, in response to the addition of an execution cycle, a NOP cycle is inserted into the decode cycle. User program end detection circuit (
5) Check NMI +41 every machine cycle.

Wait for this signal to go high. In Figure 5, 3@
It is detected that N M I 14+ changes to high level in the second machine cycle, and it is known that this machine cycle is the decoding cycle of the last instruction of the user program. After that, the user program end detection circuit +5) starts checking the DEC signal (6) from the next machine cycle (the fourth machine cycle in this example), and starts checking the DEC signal (6) in the last machine cycle of the last instruction of the user program (in this example, the fourth machine cycle). 6th machine cycle) is detected. First 4
When the DEC signal (6) is checked in the second machine cycle, it is at a low level, which indicates that this machine cycle is not the last machine cycle. Next, in the fifth machine cycle, the DEC signal +61 is at low level, so 6
Move to the second machine cycle. When the DEC signal (6) is checked in the 6th machine cycle, it is at a high level, so the user program end detection circuit (Kuji) determines that the decoding cycle for the next instruction has started, and this 6th
The second machine cycle is determined to be the last machine cycle (execution cycle) of the last instruction of the user program.

Change the user program end signal (7). By doing so, the position of the last machine cycle can be correctly determined no matter how many NOP cycles are inserted for the last instruction. In the case of Fig. 5, the in-circuit emulator control device uses the user program until the end of the 6th machine cycle as shown in the figure.
The program after that is determined to be a monitor program.

Note that in the above embodiment, the last cycle of the execution cycle is detected as the last machine cycle of the last instruction of the user program, but by using this point as a reference, the machine cycle after that point, for example, the last decode cycle, is detected. It is also possible to detect.

[Effect of the invention] As described above, according to this invention, the target CPUB is
Since the configuration is configured to output the EC signal and use this DEC signal to detect breakpoints and detect the last machine cycle of the last instruction of the user program, the target CPU that performs pipeline operation
The B in-circuit emulator also has the advantage that the above detection can be performed accurately.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of an in-circuit emulator according to an embodiment of the present invention, FIG. 2 is a system configuration diagram of a conventional in-circuit emulator, FIG. 3 is a timing chart showing the operation of a conventional in-circuit emulator, and FIG. 4 and 5 are timing charts showing the operation of one embodiment of the present invention. In the figure, (3) is an instruction address, and (4) is an NMI signal. (5) is the user program end detection circuit, (6) is the decode signal, t81 is the breakpoint detection circuit B, 1
91 is the target CPU. Note that the same line numbers in Figure 1 indicate the same or equivalent parts.

Claims (3)

[Claims] (1) A microprocessor that performs pipeline operation, which outputs a DEC signal indicating whether or not an instruction fetched based on an instruction address output in the previous machine cycle is to be decoded in the current machine cycle. processor. (2) In an in-circuit emulator equipped with a breakpoint function that stops execution of a user program when an instruction address matches a predetermined value, one An in-circuit emulator characterized by having a function for determining whether or not to accept an instruction address output in a previous machine cycle as a breakpoint. (3) In an in-circuit emulator that starts executing a monitor program immediately after stopping execution of a user program, the DE according to claim 1
An in-circuit emulator comprising a function of recognizing the last machine cycle of an instruction to be executed at the end of a user program using a C signal.