JPS56118354A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS56118354A
JPS56118354A JP2049780A JP2049780A JPS56118354A JP S56118354 A JPS56118354 A JP S56118354A JP 2049780 A JP2049780 A JP 2049780A JP 2049780 A JP2049780 A JP 2049780A JP S56118354 A JPS56118354 A JP S56118354A
Authority
JP
Japan
Prior art keywords
si3n4
opening
glass flow
film
psg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2049780A
Other languages
Japanese (ja)
Inventor
Shigeru Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2049780A priority Critical patent/JPS56118354A/en
Publication of JPS56118354A publication Critical patent/JPS56118354A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain a satisfactory glass flow effect at a relatively lower temperature, by forming an opening on an Si3N4 film after forming an opening on a PSG on an Si3N4 and removing a step by means of glass flow in H2O at the temperature of 900-1,000 deg.C. CONSTITUTION:A field oxidized film, a gate oxidized film, a polycrystalline Si gate and an n<+> layer are formed on a p type Si substrate 1, and an Si3N4 film 9 is applied thereon. After an opening is formed on a PSG7, the stepped part is removed by means of glass flow performed at the temperature of 900-1,000 deg.C and for the duration of about 30min. Then an opening is performed on the Si3N4 film 9 and an Al wiring 10 is applied. With such an arrangement, because the glass flow can be performed at a relatively lower temperature using water vapor, not only any undesirable effects to be caused by the increase in the depth of the diffusion layer can be prevented but also the possible breakdown of the Al wirings can be prevented by virtue of smoother surface of the PSG. Moreover, because of the intervention of the Si3N4, the P diffusion from the PSG can be prevented.
JP2049780A 1980-02-22 1980-02-22 Preparation of semiconductor device Pending JPS56118354A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2049780A JPS56118354A (en) 1980-02-22 1980-02-22 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2049780A JPS56118354A (en) 1980-02-22 1980-02-22 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56118354A true JPS56118354A (en) 1981-09-17

Family

ID=12028790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2049780A Pending JPS56118354A (en) 1980-02-22 1980-02-22 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56118354A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62262461A (en) * 1986-05-09 1987-11-14 Agency Of Ind Science & Technol Manufacture of semiconductor device
JPH03173126A (en) * 1989-11-30 1991-07-26 Mitsubishi Electric Corp Semiconductor device of multilayer film structure and its manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62262461A (en) * 1986-05-09 1987-11-14 Agency Of Ind Science & Technol Manufacture of semiconductor device
JPH03173126A (en) * 1989-11-30 1991-07-26 Mitsubishi Electric Corp Semiconductor device of multilayer film structure and its manufacture

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