JPS62262461A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the generation of a fixed charge in a gate oxide film against radiation irradiation by a method wherein, in the case of the formation of an MOS Tr on a substrate, all the treatment processes following the formation of the gate oxide film are executed at about 950 deg.C less. CONSTITUTION:A field oxide film 2 is formed on the surface of a P-type Si substrate 1 by a selective oxidation method and thereafter, a gate oxide film 3 is formed on the substrate surface which is used as an element region at about 900 deg.C by a dry oxidation method. Then, boron ions are implanted in a channel region 4 and after a poly Si film is deposited on the whole surface by a vapor growth method, an impurity diffusion of phosphorus is performed at about 900 deg.C. After a gate electrode 5 is formed, a source region 6 and a drain 7 are formed using this gate electrode as a mask, an interlayer insulating film 8 is deposited and a reflow is performed at 950 deg.C or less in an atmosphere of gas mixed with vapor. Then, electrodes 9, 10 and 11 are formed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a MOS type (disconnected gate type) semiconductor device, and in particular to a method for manufacturing a semiconductor device with enhanced radiation resistance. Regarding the manufacturing method.

(Prior Art) The conventional method for manufacturing MOS integrated circuits is to first form a field oxide film on the surface of, for example, a P-type silicon substrate by selective oxidation, and then dry oxidize the surface of the substrate, which will become the element region. A thick film (S102 film) is formed by the method. Next, MO to be formed in the above element area
S) Injection of impurity ions into the channel region to control the threshold voltage of the transistor.
゛) : Do Mi i. Next, a polycrystalline silicon film is deposited on the entire surface of the oxide film by vapor phase growth, and then phosphorous impurity is diffused at around 900°C. Next, a dirt electrode is formed by turning, and using this dirt electrode as a mask, for example, arsenic ions are implanted to form an N+ type source region and a drain region. Next, after depositing an interlayer insulating film over the entire surface, refrigeration is performed by heat treatment at 950° C. or higher in a N2 atmosphere. Next, a contact hole is opened, an aluminum film is deposited on the entire surface, and then electrodes and wiring are formed by patterning.

In this way, the planarization of the upper surface of the glabella insulating film is improved by performing the heat treatment at a high temperature of 950° C. or higher after forming the interlayer insulating film.

By the way, when a MOS (MOS) transistor is irradiated with radiation such as gamma rays, fixed charges accumulate in the oxide film and surface levels are formed, causing the dirt threshold voltage to fluctuate and making the transistor more likely to malfunction. The heat treatment after forming the gate oxide film is performed at a temperature of around 900° C. or lower, and the reason for this will be described below. That is, if the re-opening process after forming the interlayer insulating film is performed in an N2 atmosphere that does not contain hydrogen as in the past, the distance in the oxide film and at the oxide film/silicon interface is
Since the distance is inappropriate for bonding with a stable bond angle (144°), 5
It forms a to-oH bond and is in a stable state. However, if the treatment is carried out at a high temperature of 950°C or higher as mentioned above and in an atmosphere that does not contain hydrogen (or has a low hydrogen content), as shown in the previous equation, 8l-0-
Since an 8t bond (this is not a bond with a stable bond angle) is formed, the bond is easily broken when exposed to radiation, resulting in deterioration into an oxide film that easily generates fixed charges. .

However, in order to strengthen the radiation resistance of a MOS (MOS) transistor in this way, if the refrigeration process after forming the interlayer insulating film is not performed at a high temperature of 950°C or higher, the upper surface of the interlayer insulating film must be sufficiently flattened. This results in problems such as the metal electrodes and metal wiring having large step differences in parts, making them more likely to be cut.

(Problems to be Solved by the Invention) The present invention solves the above-mentioned contradictory problems regarding the heat treatment temperature for enhancing radiation resistance and the heat treatment temperature for flattening in the final heat treatment step before metal wiring formation. This was developed to solve this problem, and it is an insulated gate type semiconductor device that can manufacture MOS transistors with enhanced radiation resistance and whose insulating film is sufficiently flattened before forming metal wiring and metal T & electrodes. The purpose is to provide a manufacturing method.

[Structure of the Invention] (Means for Solving the Problems) The method for manufacturing an MO8 type semiconductor device of the present invention is such that when forming an MO8 type transistor on a semiconductor substrate, all steps after the formation of an oxide film are performed. The heat treatment process is carried out at a temperature of about 950° C. or lower, and is carried out before the formation of metal wiring and metal electrodes. be.

(Function) By performing the heat treatment process after forming the dirt oxide film at a temperature of about 950°C or lower, the generation of fixed charges in the oxide film due to radiation irradiation is reduced, and the final heat treatment process, which is the refrigeration process of the insulating film, is reduced. about 950℃'0. <Example) - i Hereinafter, an example of the method of the present invention with reference to the drawings -
This will be explained in detail with reference to the first manufacturing process diagram of the MO8 type integrated circuit shown in FIGS. 1(a) to (d). First, for example, P
After a field oxide film 2 is formed on the surface of a shaped silicon substrate 1 by selective oxidation, a dirt oxide film 3 having a thickness of about 250× is formed on the surface of the substrate, which will become an element region, by dry oxidation at about 900°C. Next, in order to control the threshold voltage of the hros transistor to be formed in the element region, for example, Ronio 7B is applied to the channel region 4 at an acceleration voltage of 40 kaV and a dose of 4×10 cyn.
Inject under the following conditions. Next, after depositing a polycrystalline silicon film about 4000X on the entire surface by vapor phase growth method,
Perform phosphorous impurity diffusion before and after. Next, a Jf gate electrode 5 is formed by patterning the polycrystalline silicon film, and using this dirt electrode 5 as a mask, for example, arsenic ions As are accelerated at a voltage of 50 k@V and a dose of 5×.
1015c! N+ type source region 6 and drain region 7 are formed by implantation under n-2 conditions. Next, the gas phase 30
A refrigeration process is performed by heat treatment for 30 minutes. Next, after opening 72 contact holes and depositing an aluminum film on the entire surface, the electrodes 9°1j and 62 are formed by leaning.
7. Oh, ga, yo-nio.

According to the above manufacturing method, among all the heat treatments from after the formation of the f-gate oxide film to before the formation of metal electrodes and metal wiring, the temperature of 900° C., which is unstable at 5t- The number of occurrences of o-sti -1 is small, and fluctuations in the gate threshold voltage of the MOS transistor due to the generation of defined charges are suppressed. Then, the above refrigeration process was carried out at 950°C.
Since this is carried out at high temperatures before and after, the upper surface of the interlayer bonding film can be sufficiently flattened, and the steps that occur in the metal electrodes, poles, and metal wiring become smaller, making it difficult for them to be cut. In this case, since the refrigeration process is performed in an atmosphere containing N20, the decrease in stable 5l-OH bonds as described above is suppressed, and the increase in unstable 5i-o-st bonds is suppressed. Fluctuations in dart threshold voltage are suppressed.

M obtained by
As a result of investigating the fluctuation of the gate threshold voltage when irradiating a gamma head of 1 O-rad, for example, with a source voltage of 1,500 V, a drain voltage, and a substrate voltage of Ov given to the dart voltage,
While the conventional method had a fluctuation of about 1.2 V, the method of this embodiment suppressed Vlo to a small fluctuation of about 5 V (less than half that of the conventional method).

Furthermore, FIG. 2 shows the results of investigating the dependence of gate threshold voltage fluctuations on the temperature in the refill process (refill port temperature) due to the above-mentioned 10 rad gamma ray irradiation. From this figure, the rift opening temperature is 900℃~10
MOS by conventional methods over a range of 00 °C)
Characteristics of MOS transistors before the reflow process according to the conventional method of the present invention or the method of the above embodiment, and after the reflow process by heat treatment at 950° C. for 30 minutes in an atmosphere containing N20 according to the method of the above embodiments, compared to transistors. 9 in N2 atmosphere by conventional method.
The results show the characteristics after a reflow process by heat treatment at 50° C. for 30 minutes. From this result, 3 670c caused by stretching vibration of stable 5t-OH bond
It can be seen that the absorption peak appearing at the wave number of In 2 decreases less due to the heat treatment in the N20 atmosphere in the above example than the decrease due to the heat treatment in the N2 atmosphere in the conventional method. This decrease in absorption peak is due to
Reduction of stable 5t-oH bonds and thus unstable 5i-
This means an increase in 0-3i coupling, and the smaller the decrease in the absorption peak, the more suppressed is the fluctuation in the r-to threshold voltage.

Next, another embodiment of the method of the present invention will be described with reference to the manufacturing process diagrams shown in FIGS. 4(a) to 4(d).

This embodiment differs from the previous embodiments in that (1) after the field oxide film 2 is formed, a dummy oxide film 4o is formed on the substrate surface in the element region by a dry oxidation method, and a channel is passed through the dummy oxide film 4o. Impurity ions are implanted into region 4 for threshold voltage control, followed by heat treatment at around 900°C for about 30 minutes in a N2 atmosphere, and further, for example, by wet etching by immersion in 4F (concentrated ammonium) solution. Removal of the dummy oxide film 40 (2) Next, a dirt oxide film 3 with a thickness of about 250× was formed on the substrate surface in the element region by dry oxidation at around 900° C. for 30 minutes as in the above embodiment. Since impurity ion implantation for threshold voltage control is not performed afterwards, the problem of damage remaining on the dirt oxide film due to this ion implantation does not occur.

In addition, the method of the present invention is MO8! Not limited to integrated circuits, MOs with a small number of MOS transistors on the same semiconductor substrate
It is applicable to the manufacture of 8-type semiconductor devices.

[Effects of the Invention] As described above, according to the method for manufacturing an MO8 type semiconductor device of the present invention, fluctuations in the gate threshold voltage are suppressed to a small level with respect to radiation irradiation, and the insulating film before metal wiring and metal electrodes are formed. It is possible to realize a MOS (MOS transistor) transistor in which the metal wiring is sufficiently planarized and the metal wiring etc. are not likely to be cut, and it is possible to manufacture an MO8 type semiconductor device with enhanced radiation resistance at a high yield.

[Brief explanation of drawings]

FIG. 1 is a characteristic diagram showing the MO8 type inventive method according to an embodiment of the present invention method and a conventional method, and FIG. 3 is a characteristic diagram showing the Fourier transform infrared spectrum of the gate oxide film of an MO8 type transistor according to the present invention method. FIG. 4 is a characteristic diagram showing the state of change before and after the interlayer insulating film reflow process between the conventional method and the conventional method, and FIG. 4 is a diagram showing the manufacturing process according to another embodiment of the method of the present invention. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 3... Dirt oxide film, 5... Dirt electrode, 6...
- Source region, 7... Drain region, 8... Interlayer insulating film, 9°10, 11-... Metal electrode, 40... Dummy oxide film. Engineer's armpit person, engineer's end technique wrinkle) to nine lengths, each taka difference - Figure 1 Figure 2 Figure 3 - Figure 4

Claims (3)

[Claims] (1) When forming a MOS transistor on a semiconductor substrate, all heat treatment steps after forming the gate oxide film are performed for approximately 95 minutes.
1. A method for manufacturing a semiconductor device, characterized in that the final heat treatment step before forming metal wiring and metal electrodes is carried out at 0° C. or lower in a gas atmosphere containing water vapor. (2) Among all the heat treatment steps after forming the gate oxide film, the final heat treatment step, the reflow step for the interlayer insulating film, is performed at about 950°C, and the other heat treatment steps are performed at about 900°C or lower. A method for manufacturing a semiconductor device according to claim 1. (3) A dummy oxide film is formed before the formation of the gate oxide film, channel ions are implanted through the dummy oxide film for controlling the threshold voltage of a MOS transistor, and then the dummy oxide film is removed. A method for manufacturing a semiconductor device according to claim 1 or 2.