KR0179562B1 - Method of manufacturing protection layer of semiconductor device - Google Patents
Method of manufacturing protection layer of semiconductor device Download PDFInfo
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- KR0179562B1 KR0179562B1 KR1019950069456A KR19950069456A KR0179562B1 KR 0179562 B1 KR0179562 B1 KR 0179562B1 KR 1019950069456 A KR1019950069456 A KR 1019950069456A KR 19950069456 A KR19950069456 A KR 19950069456A KR 0179562 B1 KR0179562 B1 KR 0179562B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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Abstract
본 발명은 반도체 소자의 보호막(passivation layer) 제조방법에 관한 것으로, 보다 구체적으로는, 보호막의 수소 이온의 침투를 방지하여 소자의 전기적 특성이 안정된 반도체 소자의 보호막 제조방법에 관한 것으로, 본 발명에 따르면, 반도체를 구성하는 소자가 구비된 반도체 기판 상에 소자를 보호하기 위한 보호막 형성 공정시 질화막 또는 산화막에서의 수소 이온의 침투를 방지하기 위하여 산화막 상부에 인 원자를 이온 주입하여 이후의 질화막 형성 공정시 수소이온의 침투를 방지할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a passivation layer of a semiconductor device, and more particularly, to a method of manufacturing a passivation layer of a semiconductor device, in which penetration of hydrogen ions into the passivation film is prevented, In order to prevent penetration of hydrogen ions in the nitride film or oxide film in the protective film forming process for protecting the elements on the semiconductor substrate having the elements constituting the semiconductor, phosphorus atoms are ion-implanted in the upper portion of the oxide film, It is possible to prevent permeation of hydrogen ions at the time.
Description
제1도는 종래의 반도체 소자의 보호막 제조방법을 설명하기 위한 도면.FIG. 1 is a view for explaining a conventional method of manufacturing a protective film for a semiconductor device; FIG.
제2도는 본 발명의 실시예 1에 따른 반도체 소자의 보호막 제조방법을 설명하기 위한 도면.FIG. 2 is a view for explaining a method of manufacturing a protective film of a semiconductor device according to Embodiment 1 of the present invention. FIG.
제3도는 본 발명의 실시예 2에 따른 반도체 소자의 보호막 제조방법을 설명하기 위한 도면.FIG. 3 is a view for explaining a method for manufacturing a protective film for a semiconductor device according to Embodiment 2 of the present invention. FIG.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
16 : 플라즈마 보조 산화막 17 : TEOS 산화막16: Plasma assisted oxide film 17: TEOS oxide film
18 : 플라즈마 보조 질화막 26 : 부하 저항용 산화막18: plasma-assisted nitride film 26: oxide film for load resistance
27 : TEOS 오존 산화막 30 : 보호용 질화막27: TEOS ozone oxide film 30: protective nitride film
본 발명은 반도체 소자의 보호막(passivation layer) 제조방법에 관한 것으로 보다 구체적으로는, 보호막의 수소 이온의 침투를 방지하여 소자의 전기적 특성이 안정된 반도체 소자의 보호막 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a passivation layer of a semiconductor device, and more particularly, to a method for fabricating a passivation layer for a semiconductor device in which penetration of hydrogen ions into the passivation film is prevented and electrical characteristics of the device are stabilized.
일반적으로, 보호막 즉, 패시베이션막은 최후의 금속 배선 공정 이후, 웨이퍼 전면에 증착되는 절연막으로서, 이후의 어셈블리 및 팩키지 공정시 기계적 화학적 손상을 방지하기 위하여 증착된다.Generally, a passivation film, that is, a passivation film, is an insulating film deposited on the entire surface of the wafer after the final metallization process, and is deposited to prevent mechanical and chemical damage during subsequent assembly and packaging processes.
이러한 보호막으로는 PSG막 또는 질화막 등과 같이, 습기, 이동 이온(mobil ion)등을 포획할 수 있는 막 등이 이용된다.As such a protective film, a film capable of capturing moisture, mobile ions and the like such as a PSG film or a nitride film is used.
여기서, 종래의 반도체 소자의 보호막 제조방법에 대하여 첨부한 도면을 통하여 자세히 살펴보면, 제1도에 도시된 바와 같이, 게이트 산화막(도시되지 않음), 게이트 전극(2), 소오스(3), 드레인(4) 및 비트라인(5)이 형성되어 있는 반도체 기판(1) 상부에 상기 형성된 소자를 보호하기 위하여 웨이퍼 상부에 실란(SiH4) 가스의 분위기에서 실리콘과 산소의 비율을 1:2로 결합시킨 산화막(6)을 형성하고, 그 상부에 유동하는 금속 이온에 대한 장벽효과가 우수한 질화막(7)을 암모니아(NH3) 가스를 이용하여 형성한다.As shown in FIG. 1, a gate oxide film (not shown), a gate electrode 2, a source 3, a drain (not shown) In order to protect the device formed on the semiconductor substrate 1 on which the bit lines 5 and the bit lines 5 are formed, a silicon-oxygen ratio of 1: 2 is formed in an atmosphere of silane (SiH 4 ) gas on the wafer An oxide film 6 is formed, and a nitride film 7 having an excellent barrier effect against metal ions flowing on the oxide film 6 is formed using ammonia (NH 3 ) gas.
그러나, 상기와 같이, 반도체 소자를 보호하기 위한 보호막으로서, 산화막과 질화막을 형성하게 되면, 상기 산화막과 질화막을 구성하는 실란 가스와 암모니아 가스에 함유되어 있는 수소 이온이 RF(radio frequency) 전원에 의하여 하부에 형성되어 있는 반도체 소자 내부로 확산 침투되어, 확산 영역에서의 반전(inversion) 또는 문턱 전압(threshold voltage)이 변이되는 문제점이 발생하였으며, SRAM의 경우, 침투하는 수소이온에 의하여 부하 저항이 감소되어 소자의 특성을 저하시키게 되는 문제점이 발생하였다.However, as described above, when the oxide film and the nitride film are formed as the protective film for protecting the semiconductor device, hydrogen ions contained in the silane gas and the ammonia gas constituting the oxide film and the nitride film are separated by an RF The inversion or the threshold voltage in the diffusion region is changed due to the diffusion into the semiconductor device formed in the lower portion. In the case of the SRAM, the load resistance is reduced by the penetrating hydrogen ions Resulting in deterioration of the characteristics of the device.
따라서, 본 발명은 반도체 소자의 보호막 형성시, 수소 이온의 확산 침투되는 현상을 방지하여, 소자의 확산 영역의 반전 현상 및 문턱 전압이 변이되는 문제점을 방지하여 소자의 특성을 향상시킬 수 있는 반도체 소자의 보호막 제조방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device capable of preventing the phenomenon of diffusion of hydrogen ions during the formation of a protective film of a semiconductor device and preventing the problem of reversal of the diffusion region of the device and variation of threshold voltage, And to provide a method for manufacturing a protective film of the same.
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 반도체 소자가 형성되어 있는 기판 상에 소자 보호용 산화막과 질화막을 적층하여 이루어지는 반도체 소자의 보호막 형성방법에 있어서, 상기 산화막과 질화막을 증착하는 단계 사이에 TEOS 산화막을 증착하고, 이 TEOS 산화막에 인 원자를 이온 주입하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming a protective film for a semiconductor device, the method comprising the steps of: depositing an oxide film and a nitride film; And a phosphorus atom is implanted into the TEOS oxide film.
또한, 본 발명은, 에스램 소자가 구비된 반도체 기판 상부에 부하 저항용 산화막을 형성하는 단계; 상기 부하 저항용 산화막 상부에 TEOS 오존 산화막을 형성하는 단계; 상기 TEOS 오존 산화막 상부에 인 원자를 이온 주입하는 단계; 상기 결과물을 열처리하는 단계; 및 상기 열처리딘 결과물 상부에 보호용 질화막을 증착하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an oxide film for load resistance on a semiconductor substrate provided with an Lambda device; Forming a TEOS ozone oxide film on the oxide film for load resistance; Implanting phosphorus atoms on the TEOS ozone oxide film; Heat treating the resultant; And depositing a protective nitride film on the resultant of the heat treatment.
이하 본 발명의 양호한 실시예를 첨부 도면을 참고하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[실시예 1][Example 1]
첨부한 제2도는 본 발명의 실시예 1에 관련되는 반도체 소자의 보호막 형성방법을 나타내는 도면이다.FIG. 2 is a view showing a method of forming a protective film for a semiconductor device according to Example 1 of the present invention.
우선, 제2도에 도시된 바와 같이, 게이트 산화막(11), 게이트 전극(12), 소오스(13), 드레인(14) 및 비트라인(15)이 형성되어 있는 반도체 기판(10) 상부에 플라즈마 보조 산화막(16)을 약 1000 내지 3000의 두께로 형성한다. 이 때, 상기 플라즈마를 발생시키기 위한 RF 전원은 동일한 비율의 고전력과 저전력의 이중 전원을 사용하고, 플라즈마 증착 챔버의 온도를 약 350 내지 450로 하고, 상기 실란과 산화 질소의 비율을 변화시켜 굴절률이 약 1.4 내지 1.7 정도가 되도록 유지하고, 스트레스는 약 1.6 내지 1.9 dyne/가 가해지도록 하여 형성한다. 상기 플라즈마 산화막(16)은 산소의 비율보다 실리콘의 비율이 증가하여 결합에 참여하지 않는 잉여 실리콘이 댕글링 본드를 이루어 실란 가스에서 이탈되는 수소이온을 상기 실리콘의 댕글링 본드가 포획하는 역할을 하게 되서 수소 이온이 반도체 기판속으로 침입하는 것을 방지할 수 있다.First, as shown in FIG. 2, on the semiconductor substrate 10 on which the gate oxide film 11, the gate electrode 12, the source 13, the drain 14 and the bit line 15 are formed, The auxiliary oxide film 16 is deposited to a thickness of about 1000 to 3000 . At this time, the RF power source for generating the plasma uses a high power and a low power dual power source of the same ratio, and the temperature of the plasma deposition chamber is about 350 to 450 And the refractive index is maintained at about 1.4 to 1.7 by changing the ratio of the silane and the nitrogen oxide, and the stress is about 1.6 to 1.9 dyne / As shown in FIG. In the plasma oxide film 16, the ratio of silicon to oxygen is increased, so that surplus silicon that does not participate in bonding plays a role of capturing the hydrogen ions separated from the silane gas by the dangling bonds of the silicon, So that hydrogen ions can be prevented from entering into the semiconductor substrate.
이어서, 상기 플라즈마 보조 산화막(16) 상부에 공지의 방법으로 TEOS 산화막(17)을 약 3000 내지 5000의 두께로 증착하고 상기 증착된 TEOS 산화막(17) 상부에 인(P) 원자를 11015 11019원자/의 농도로, 100 내지 300KeV의 에너지 범위로 이온 주입한 다음, 질소 분위기 하에서 약 400 내지 600로 약 30 내지 60분간 열처리한다. 이 때, 상기 인 원자를 이온 주입하는 것은, 가전자수가 5인 인 원자가 후속 공정인 질화막의 형성시 수소 이온을 포획하도록 하기 위하여 이온주입한다.Subsequently, a TEOS oxide film 17 is deposited on the plasma-assisted oxide film 16 by a known method to a thickness of about 3000 to 5000 (P) atom is deposited on the deposited TEOS oxide film 17 to a thickness of 1 10 15 One 10 19 atom / At an energy range of 100 to 300 KeV, and then implanted under a nitrogen atmosphere at a dose of about 400 to 600 For about 30 to 60 minutes. At this time, the ion implantation of the phosphorus atoms is performed by ion implantation in order to trap hydrogen ions in the formation of a nitride film, which is a subsequent step of atomic valence electrons.
그리고, 상기 TEOS 산화막(17) 상부에 실란, 암모니아 및 질소 가스 분위기에서 플라즈마 보조 산화막(18)을 5000 내지 8000두께로 형성한다. 이 때, 스트레스는 약 1.6 내지 1.9 dyne/이 가해지도록 한다.Then, the plasma-assisted oxide film 18 is deposited on the TEOS oxide film 17 in an atmosphere of silane, ammonia, and nitrogen gas at 5000 to 8000 . At this time, the stress is about 1.6 to 1.9 dyne / .
[실시예 2][Example 2]
첨부한 제3도는 본 발명의 실시예 1에 관련되는 반도체 소자의 보호막 형성방법을 나타내는 도면이다.FIG. 3 is a view showing a method of forming a protective film for a semiconductor device according to Example 1 of the present invention.
우선, 제3도에 도시된 바와 같이, 에스램 소자를 구성하는 게이트 산화막(21), 게이트 전극(22), 소오스(23), 드레인(24) 및 비트라인(25)가 형성되어 있는 반도체 기판(20) 상부에 부하 저항용 산화막(26)을 형성하고, 그 상부에 TEOS 오존 산화막(27)을 형성한다.First, as shown in FIG. 3, a semiconductor substrate 21 on which the gate oxide film 21, the gate electrode 22, the source 23, the drain 24, and the bit line 25, An oxide film 26 for load resistance is formed on the upper surface of the substrate 20, and a TEOS ozone oxide film 27 is formed thereon.
이어서, 상기 TEOS 오존 산화막(27) 상부에 인(P) 원자를 11013 11019원자/의 농도로, 30 내지 50KeV의 에너지 범위로 이온 주입한 다음, 약 800 내지 950로 약 30 내지 60분간 열처리한다. 이 때, 상기 인 원자를 이온 주입하는 것은, [실시예1]과 동일한 효과로서, 가전자수가 5인 인 원자가 후속 공정인 질화막의 형성시 수소 이온을 포획하도록 하기 위하여 이온주입한다.Subsequently, phosphorus (P) atoms are formed on the TEOS ozone oxide film 27 by 1 10 13 One 10 19 atom / At an energy range of 30 to 50 KeV and then implanted at a dose of about 800 to 950 For about 30 to 60 minutes. At this time, ion implantation of the phosphorus atoms is effected in the same manner as in [Example 1], in order to trap hydrogen ions during the formation of a nitride film which is a subsequent step of atomic valence of five valence electrons.
그리고, 전체 구조물 상부에 BPSG막(28), 금속층(29), 보호용 질화막(30)을 순차적으로 형성하여, 에스램 소자의 열화를 방지하고, 부하 저항의 고저항화를 이룰 수 있다.Then, the BPSG film 28, the metal layer 29 and the protective nitride film 30 are sequentially formed on the entire structure to prevent deterioration of the ESRAM element and increase the resistance of the load resistance.
이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 반도체를 구성하는 소자가 구비된 반도체 기판 상에 소자를 보호하기 위한 보호막 형성 공정시 질화막 또는 산화막에서의 수소 이온의 침투를 방지하기 위하여 산화막 상부에 인 원자를 이온 주입하여 이후의 질화막 형성 공정시 수소이온의 침투를 방지할 수 있는 효과가 있다.As described in detail above, according to the present invention, in order to prevent penetration of hydrogen ions in a nitride film or an oxide film in a protective film forming step for protecting an element on a semiconductor substrate provided with elements constituting a semiconductor, Atoms can be implanted to prevent penetration of hydrogen ions in the subsequent nitridation film forming process.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, the present invention can be variously modified without departing from the gist of the present invention.
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