JPS6139751B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device including an ion implantation step, and particularly to a method that is effective when applied to so-called channel doping in which the impurity concentration in a channel portion of a MIS type FET is controlled by ion implantation.

In MIS type integrated circuits (ICs), a so-called channel doping technique is generally adopted in which impurity ions are implanted into the channel part in order to adjust the gate threshold of MIS FETs, and this technique is especially used for enhancement type FETs.
The above technology is indispensable for ICs that include multiple types of FETs with different gate thresholds, such as E/D mode MIS type ICs that use a depletion type FET as a driver and a depletion type FET as a load. Normally, this channel doping process is carried out by implanting ions through a thermal oxide film as a gate insulating film, but impurities are removed during processes that involve high-temperature heating such as ion implantation damage annealing and thermal diffusion after this process. Particularly in the case of boron implantation, which is frequently used, the distribution coefficient of boron into the thermoset film is large, so the impurity concentration on the substrate surface is significantly lower than the predicted value, and the gate is not as designed. There was a problem that the threshold value could not be obtained.

Therefore, the present invention provides a method that can prevent redistribution of impurities, particularly a decrease in surface concentration, due to post-implantation heat treatment in such an ion implantation process.

The method of manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device using a direct thermal nitride film formed on a silicon surface.
The method includes a step of performing heat treatment after ion implantation into the FET formation region, and is characterized in that the thermal nitride film is left in the MIS type FET formation region to form at least a part of the gate insulating film. This will be explained in detail.

A direct thermal nitride film is formed by heating a silicon substrate to a high temperature of approximately 900 to 1300°C in an atmosphere of nitrogen or a nitrogen compound gas such as ammonia or hydrazine to cause a direct reaction and growth. It is. It has been confirmed that this silicon nitride film formed by direct thermal nitridation has an excellent masking effect against the diffusion of impurities. The present invention takes advantage of the properties of this direct thermal nitride film, implants impurity ions into the silicon substrate through the silicon nitride film, and performs post-implantation heat treatment to redistribute the impurities, particularly in the green-free film on the surface of the silicon substrate. This prevents relocation to. This makes it possible to prevent a decrease in surface concentration during heat treatment, and when applied to channel doping, it is possible to ensure an accurate gate threshold value expected from the amount of ion implantation. Furthermore, it has been confirmed that the thermal silicon nitride film has an extremely excellent passivation effect for preventing surface contamination, and the present invention is also effective in preventing surface contamination and unnecessary reactions associated with ion implantation and its pre- and post-treatments. Much better effects can be expected than ion implantation through a thermal oxide film.

An example of the manufacturing process of a MIS type FET to which the present invention is applied will be described below with reference to the drawings.

First, as shown in FIG. 1a, the MIS type FET forming region of the green-proofing film 2 on the surface of the P-type silicon substrate 1 is removed to open a window. Next, this substrate is heated to about 900 to 1300 ℃ in a nitriding atmosphere such as nitrogen or ammonia, and the exposed surface of the silicon substrate is directly thermally nitrided to form a silicon nitride film. This direct nitridation occurs only on the exposed portions of silicon and does not occur on the surface of the green-free film 2. Therefore, as shown in FIG. 1b, a silicon nitride film 3 is formed within the window of the anti-green film 2. Its thickness is, for example, 100 Å. Thereafter, boron ions are implanted into the substrate 1 through the silicon nitride film 3.

Arrow 4 in FIG. 4b represents the boron ion B ⁺ beam. Since the silicon nitride film 3 is extremely thin, a relatively low implantation energy of about 46 KeV is sufficient. The field film 2 having a thickness of several thousand angstroms acts as a mask for ion implantation, and as a result, the ion implantation layer 5 is formed only in the element formation region.

Next, this substrate is subjected to heat treatment, which is exactly the same process as conventionally performed, at a temperature of around 1000℃ for the purpose of recovering implantation damage and activating implanted impurities. Heating is performed for about a minute.

In this example, there is a thermal diffusion step that involves high-temperature heating, and in such a case, the above-mentioned heat treatment may be omitted.

In such a heat treatment process, the silicon nitride film 3 covering the surface of the implanted region exhibits a strong masking property against the diffusion of impurities and does not suck out impurities unlike a thermal oxide film. There is no problem of surface concentration changes, especially decreases. Also, before and after the ion implantation process, various cleaning processes for the substrate surface, such as acid treatment,
However, since the interface between the silicon nitride film 3 and the silicon substrate 1 caused by the thermal nitriding reaction is never exposed to the processing solution or the outside air, there is no risk of interface contamination unlike in the case of CVD. Furthermore, an additional advantage is that the intrusion of contaminants such as alkali ions can be completely prevented due to the denseness and good masking properties of the silicon nitride film 3 itself.

Next, to ensure the necessary thickness for the gate insulation film
A green-proof film 6 such as silicon dioxide is deposited by the CVD method, and then a polycrystalline silicon film 7 as a gate electrode material is formed (FIG. 1c).

The subsequent steps are the same as the conventional ones, so to briefly explain, as shown in FIG.
After sequentially etching 3, a silicate glass (PSG) film 8 which serves as a diffusion source for n-type impurities is deposited, and the whole is heated to around 1000°C to diffuse the area adjacent to the PSG film 8 into the substrate 1. , n-type source and drain regions 9 and 10 are formed. Thereafter, as shown in FIG. 1e, after electrode windows are formed in the PSG film 8, an electrode metal such as aluminum is deposited and patterned to form source and drain electrodes 11 and 12, thereby completing the device.

In the MIS type FET according to this embodiment, since the boron implanted region 5 formed in the channel part is covered with a thermal silicon nitride film, there is little variation in boron concentration, and therefore an accurate gate threshold value can be secured according to the amount of boron implanted. It is.

According to experiments, a thermal nitride film with a thickness of 100 Å was formed on each (100) P-type silicon substrate of 3 to 5 Ωcm, and B ⁺ ions were irradiated with 5 × 10 ¹³ at 40 KeV on top of the thermal nitride film.
cm ^-2 is implanted to form an n ⁺ type diffusion region adjacent to each implanted region, and annealed at 1100°C for 30 minutes, an avalanche breakdown occurs at the n ^{+ P} junction between this n ⁺ region and the substrate. When using a thermal nitride film, the voltage is
6.6V±0.2V, −8.7V± when using thermal oxide film
It was 0.5V. The lower breakdown voltage after ion implantation through the thermal nitride film means that the surface concentration of the boron implanted region does not decrease much even after annealing. Further, the above breakdown voltage is a value obtained by measuring at multiple locations within a single silicon wafer, and it can be seen that the variation is smaller when ions are implanted through a thermal nitride film.

From the above experimental results, it is clear that the method of the present invention is effective in ensuring the desired implantation concentration by ion implantation until the final process, and is especially effective in strictly setting the gate threshold when applied to channel doping technology as in the above embodiment. It is clear that it is extremely useful in that it can be done.

In addition to the above-mentioned effects, the present invention provides the effect of directly preventing surface contamination, unnecessary reactions, etc. by the thermal silicon nitride film, and its practical effects are extremely large. It is.

[Brief explanation of the drawing]

FIGS. 1a to 1e are cross-sectional views of a substrate showing steps in an embodiment of the present invention. 3... Direct thermal nitride film, 4... Ion beam, 5
...Boron implanted region, 7...Polycrystalline silicon film.

Claims (1)

[Claims] 1 Includes a step of performing heat treatment after ion implantation into the MIS type FET formation region through a direct thermal nitride film formed on the silicon surface, leaving the thermal nitride film in the MIS type FET formation region and forming the gate insulating film. A method for manufacturing a semiconductor device, characterized in that at least a part of the semiconductor device is manufactured.