JPS5611700A - Correcting system for control memory error - Google Patents

Correcting system for control memory error

Info

Publication number
JPS5611700A
JPS5611700A JP8671879A JP8671879A JPS5611700A JP S5611700 A JPS5611700 A JP S5611700A JP 8671879 A JP8671879 A JP 8671879A JP 8671879 A JP8671879 A JP 8671879A JP S5611700 A JPS5611700 A JP S5611700A
Authority
JP
Japan
Prior art keywords
error
bit
control memory
correction
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8671879A
Other languages
Japanese (ja)
Inventor
Joji Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8671879A priority Critical patent/JPS5611700A/en
Publication of JPS5611700A publication Critical patent/JPS5611700A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To enable the continuity of job through immediate correction of bit error, by monitoring the loading of microprogram and writing in the correction bit data to the control memory of processor at error bit detection.
CONSTITUTION: The data in the floppy disc 1 is loaded to the control memory 4 of processor via the address register 3 with the loader 2 including the monitor. Further, when error bits are detected at the parity check circuit 7, the error correction circuit 8 retrieves the address of the memory 4 producing the bit errors and picks up the instruction corresponding to the address from the disc 1 for inverted bit processing, then the bit data in the memory 4 is rewritten for the correction. Accordingly, the error of the control memory is immediately corrected and the job by the processor can be continued.
COPYRIGHT: (C)1981,JPO&Japio
JP8671879A 1979-07-09 1979-07-09 Correcting system for control memory error Pending JPS5611700A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8671879A JPS5611700A (en) 1979-07-09 1979-07-09 Correcting system for control memory error

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8671879A JPS5611700A (en) 1979-07-09 1979-07-09 Correcting system for control memory error

Publications (1)

Publication Number Publication Date
JPS5611700A true JPS5611700A (en) 1981-02-05

Family

ID=13894656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8671879A Pending JPS5611700A (en) 1979-07-09 1979-07-09 Correcting system for control memory error

Country Status (1)

Country Link
JP (1) JPS5611700A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6820047B1 (en) * 1999-11-05 2004-11-16 Kabushiki Kaisha Toshiba Method and system for simulating an operation of a memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6820047B1 (en) * 1999-11-05 2004-11-16 Kabushiki Kaisha Toshiba Method and system for simulating an operation of a memory

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