JPS5635253A - Control storage error recovery processing system - Google Patents

Control storage error recovery processing system

Info

Publication number
JPS5635253A
JPS5635253A JP11112879A JP11112879A JPS5635253A JP S5635253 A JPS5635253 A JP S5635253A JP 11112879 A JP11112879 A JP 11112879A JP 11112879 A JP11112879 A JP 11112879A JP S5635253 A JPS5635253 A JP S5635253A
Authority
JP
Japan
Prior art keywords
error
control storage
occurrence
data
transmitted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11112879A
Other languages
Japanese (ja)
Other versions
JPS6041373B2 (en
Inventor
Toshio Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54111128A priority Critical patent/JPS6041373B2/en
Publication of JPS5635253A publication Critical patent/JPS5635253A/en
Publication of JPS6041373B2 publication Critical patent/JPS6041373B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To reduce greatly the chance for occurrence of the error, by performing the rewriting for recovery via the source data held by the service processor in case an error arises in the control storage which uses no error collection code.
CONSTITUTION: In case the data delivered from the control storage 2 receives an error detection through the parity detector 6 during operation of the CPU1, this information is transmitted to the interface 11 of the service processor SVP7 from the detector 6. The error occurrence address is transmitted to the address register 3 via the interface 11 in order to write the initial control storage data to the error occurrence address from the source data stored in the file 10. And at the same time, the initial control storage data is transmitted to the output register 5. Then the error occurrence data is rewritten to reduce greatly the chance for occurrence of the error.
COPYRIGHT: (C)1981,JPO&Japio
JP54111128A 1979-08-30 1979-08-30 Control storage error recovery processing method Expired JPS6041373B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54111128A JPS6041373B2 (en) 1979-08-30 1979-08-30 Control storage error recovery processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54111128A JPS6041373B2 (en) 1979-08-30 1979-08-30 Control storage error recovery processing method

Publications (2)

Publication Number Publication Date
JPS5635253A true JPS5635253A (en) 1981-04-07
JPS6041373B2 JPS6041373B2 (en) 1985-09-17

Family

ID=14553146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54111128A Expired JPS6041373B2 (en) 1979-08-30 1979-08-30 Control storage error recovery processing method

Country Status (1)

Country Link
JP (1) JPS6041373B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS597548U (en) * 1982-07-07 1984-01-18 和泉電気株式会社 Composite relay device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS597548U (en) * 1982-07-07 1984-01-18 和泉電気株式会社 Composite relay device
JPS6314360Y2 (en) * 1982-07-07 1988-04-22

Also Published As

Publication number Publication date
JPS6041373B2 (en) 1985-09-17

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