JPS6041373B2 - Control storage error recovery processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control storage error recovery processing scheme, and more particularly to error correcting code (ECC) processing.
This invention relates to a control storage efficiency recovery processing method for performing recovery processing when an error occurs in a control storage that does not use ).

The control storage part of the data processing device is the part where the control microprogram is stored, so it is configured so that hard errors are unlikely to occur, and even if a 1-bit error occurs, it is processed by ECC. Built-in 1-bit error correction function.

However, since the provision of this ECC mechanism slows down the speed and degrades performance, some models omit it. However, even in such a case, an error may occur in the control storage, so even in such a case, it is required to correct it correctly without using the ECC mechanism. Therefore, in the present invention, if an error occurs in the control storage where the ECC mechanism is omitted, it is corrected, and if the error is fixed due to a hard error etc., the data in that part is transferred to the other part of the control storage. The object of the present invention is to provide a control storage error recovery processing method configured to store microprograms in a microprogram. A control storage control method comprising a control storage, a microprogram storage means for storing the microprogram from source data in the control storage, and an error detection means for detecting the presence or absence of an error in the output of the control storage. A comparison means for comparing the output data of the storage and the source data to be written in the control storage, and a control table indicating the data storage state in the control storage of the replaceable unit of the microprogram. If an error is detected by the error detection means, the error data storage part is rewritten from outside the source data, and when the rewritten data is released, if an error also exists therein, Based on the control table, the data stored in the error occurrence part is controlled to be stored in another part of the control storage, and the control table also stores the module number and control storage of the control storage. It consists of a module control table in which flags are written and a replacement control table in which the address of the branch order of the microprogram whose module number is the branch destination address is written, and the module containing the error occurrence address is set as the branch destination. The present invention is characterized in that the branch order in question is detected using the alternation control table, and the branch destination is controlled to be changed.

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

Figure 1 shows the circuit configuration of an embodiment of the present invention, and Figure 2 shows a module that manages the usage status of the control storage.
FIG. 3 shows a replacement control table.

In the figure, 1 is a central processing unit, 2 is a control storage, 3 is an address register for control storage, 4 is a backup register for control storage, 5 is an output register, 6 is a parity detector, 7 is a service processor, 8 is a control processor that controls the service processor, 9 is a memory for the service processor, 10 is a file, 11 is an interface provided in the service processor, 15 is a module control table, and 16 is a Module relative address table 17 is a branch address table.

Although only one backup register 4 is shown, a plurality (for example, four) of backup registers 4 are provided to record the history of the address register 3. and output register 5
The parity detector 6 performs a parity check on the output data, and if an error is detected in the data,
The address recorded in the backup register Y4 above.
By examining the data, it is possible to know at which address stored in the control storage 2 the error occurred. The control processor 8 operates to control the service processor 7, and its control program is written in one file. Memory 9 is service processor 7
A memory for storing, for example, the output data of the control storage 2 and the source data written in the file 1 in this memory 9 and allowing the control processor 8 to perform functions such as comparison. It is. The file 10 contains source data for the control storage 2, a program for controlling the service processor system, a module control table to be described later, a replacement control table composed of a module relative address table and a branch address table, etc. There is.

The module control table 15 is as shown in FIG.
This is a table in which the entire memory area of the control storage is sequentially numbered for each microprogram changeable minimum unit (for example, 64 words), and displays the usage status of the module area.

This table is created when the microprogram is initially loaded. Each module has a module number and a control flag written thereon, as shown at the beginning of FIG. As shown in FIG. 2C, this control flag is composed of, for example, 8 bits, of which only the first 3 bits are used and the remaining 5 bits are reserved for the future. This control flag indicates the following status. (2) Bit 0 (A): Indicates whether the module is being used or not, and when the bit is on, it indicates that it is being used.

■Bit 1 (i): At system initialization,
This indicates whether the module is in use or not, and when the bit is on, it indicates that the module is in use or was in use.

(2) Bit 2 (E): Indicates whether or not this is an error module during system operation; when the bit is on, it indicates an error module in which an error exists.

■The value of the control flag at system initialization is
There are 16 ships displayed, and they are either of the following two types.

“CoJ: Denotes microprogram usage module.

"00": Indicates an empty module. (2) The value of the control flag during system operation is one of the following five values with 16 ships displayed.

"EO": Indicates that an error has occurred in the module in use. "80": Indicates that the module was an empty module at the time of system initialization, but is currently being used as a replacement module.

"AO": Indicates that an error occurred during use as a replacement module.

"CO": Same as the system initialization in (2) above.

"00": Same as the system initialization in (2) above.

It should be noted that the module number in the module control table indicates the replacement relationship of replacement modules, and n is set in the n module at the time of system initialization.

However, if a hard error occurs in the i module and the correct contents of the i module are transferred from the source data to this n module, these module numbers will be switched and at the same time the control flag will also be changed to one of the ones shown in (■) above. will be corrected. As a result, for the first i module, the module number changes from i to n, and the control flag changes from "CO" to "EO" branch address table 1.
7 can be easily obtained. Of course, the module relative address table 16 and branch address table 17 are similar to the module control table 15 shown in FIG.
This is also entered in File 1. Now, in FIG. 1, when the data output from the control storage 2 is parity-checked by the parity detector 6 during the operation of the central processing unit 1 and an error is detected, the data is sent from the parity detector 6 to the SVP- C.P.
The error report in the control storage 2 is transmitted to the U interface 11 and the service processor 7 .

From this, the control processor 8 reads the backup register 4 and learns the error occurrence address of the control storage 2. In order to write initial control storage data from the source data stored in the file 101 to this error occurrence address, via the SVP-CPU interface 11,
Transmit the error occurrence address to address register 3,
And the above initial control signal is input to output register 5.
The storage data is transmitted, and then a write signal is transmitted to rewrite data to the address where the error occurred. The rewritten data is then submitted and compared with the source data of file 10 to check whether the data was written correctly. If the data is written correctly as a result, the restart address of the microprogram is set and started. However, if the error cannot be repaired even after rewriting as described above, a hardware failure has occurred at the address where the error occurred in the control storage, and the address area will not be used and a free module will be searched for. Then, the data of the module including the error occurrence address is transferred from the source data of the file 10 to the vacant module. For this, the above file - 0
'Modify the module control table 15 shown in FIG. 2A with this entry below.

For the first n modules, the module number changes from n to i, and the control flag changes from "00" to "80". The alternation control table includes the module relative address table 16 shown in FIG. 3A and the branch address table 16 shown in FIG.
It is composed of an address table 17.

The module relative address table 16 records the presence or absence of microinstructions that use each module as a branch destination address, as well as relative addresses in which a list of the microinstructions is written.

In a module that is not used as a branch destination, 16 ships are displayed and "FFFF" is written in its relative address. For example, the list of microinstructions whose branch destination is the microprogram stored in the module 0 area in FIG.
0”, the module relative address
"roooo" is written in the module 0 portion of table 16. Then, a control in which a microinstruction whose branch destination is module 0 is stored in the relative address part. A list of storage addresses and their data is filled in. Of course, this alternation control table is used during the so-called initial program load (IPL), which writes the source data stored in the files of the service processor 7 to the control storage 2 of the central processing unit 1 at the time of system initialization.
It was made at the time. That is, as shown in FIG. 4, the microprogram branch order 8 includes an operation code (OPECODE) section 18-1, a module address section 18-2 for the branch destination, etc. in addition to the normal function areas CO to C3. is provided.

In the case of this plannch order, for example, OPE
Since the specific 2 bits of CODE are “1”,
By detecting this, only the branch order is detected in address order during the IPL, and then the data is arranged in the order of the branch destination address, thereby searching from the module relative address table 16 and the position side to find an empty module. For example, if module n is vacant and the module containing the above error occurrence address is module i, then in the first module n, the module number changes from n to i, and the control flag is set to "00". From “8
0". Then, at the beginning of module i, the module number changes from i to n, and the control flag changes from "CO" to "EO". Then, read the relative address at module i in the module relative address table 16 shown in FIG. Correct the address to module n. Of course, it is also possible to correct the module relative address table 16 and the branch address table 17 accordingly, thereby making it possible to correct the branch destination even more quickly.
After all, according to the present invention, when an error occurs in the control storage, the source data held by the service processor is rewritten to repair the error.

If this error is repaired at this time, the error is determined to be an interlude error and processing continues. However, if there is an error due to the above rewriting, it is determined that this is a hard error, and the control storage area where the error exists is not used, which greatly reduces the chances of an error occurring. can do. Moreover, this hard
When data is transferred from an error existing area to an empty module area, since the module control table is prepared in advance in the file, the transfer to this empty module can be performed extremely smoothly.

Furthermore, since the alternation control table is provided in the file, it is possible to correct the branch destination of the branch order in an extremely short time.

[Brief explanation of the drawing]

Fig. 1 shows the circuit configuration of an embodiment of the present invention, Fig. 2 A shows a module control table, Fig. 2 opening shows entries in the module control table, and Fig. 2 C shows entries in the module control table. The details of the control flags to be
Figure A shows the module relative address table, Figure 3 shows the branch address table, and Figure 4 shows the microprogram branch order. In the figure, 1 is a central processing unit, 2 is a control storage, 3 is an address register for control storage, 4 is a backup register for control storage, 5 is an output register, 6 is a parity detector,
7 is a service processor, 8 is a control processor that controls the service processor, 9 is a memory for the service processor, 10 is a file, 11 is an interface provided in the service processor, 15 is a module control table, 16 indicates a module relative address table, and 17 indicates a branch address table. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A control storage device comprising a control storage for storing a microprogram, a microprogram storage means for storing the microprogram from source data in the control storage, and an error detection means for detecting the presence or absence of an error in the output of the control storage. In storage control method, control and
Comparison means for comparing the output data of the storage and the source data to be entered into the control storage;
A control table is provided that indicates the data storage state in the control storage of the replaceable unit of the microprogram, and when an error is detected by the error detection means, the error data storage part is rewritten with the source data, When this rewritten data is read, if an error also exists therein, the data stored in the error occurrence part is controlled to be stored in another part of the control storage based on the control table, and Furthermore, the above control table is composed of a module control table in which the module number and control flag of the control storage are written, and an alternation control table in which the address of the branch order of the microprogram whose branch destination address is the module number is written. A control storage error recovery processing method characterized in that a branch order whose branch destination is a module containing an error occurrence address is detected by the alternation control table, and control is performed to change the branch destination.