JPS56107575A - Manufacture of semicondutor device - Google Patents
Manufacture of semicondutor deviceInfo
- Publication number
- JPS56107575A JPS56107575A JP907080A JP907080A JPS56107575A JP S56107575 A JPS56107575 A JP S56107575A JP 907080 A JP907080 A JP 907080A JP 907080 A JP907080 A JP 907080A JP S56107575 A JPS56107575 A JP S56107575A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- polycrystalline silicon
- memory cell
- oxide film
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- High Energy & Nuclear Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To obtain a memory cell stable against alpha rays by forming an electrode of constant potential on a gate electrode of a flip-flop transistor constituting the memory cell. CONSTITUTION:There are formed N type source and drain domains 103-5, 1103-7 on a P type semiconductor substrate 201, and a load resistance RL and silicon gates of transistors Q1, Q2 are formed with a polycrystalline silicon 104-1. The surface of the silicon gate is oxidized to form an oxide film 207. Then, a nitride film 208 is formed on the oxide film 207, which is then oxidized to form an oxide film 209. A polycrystalline silicon electrode 106 is formed thereon, and a gate electrode and an electrostatic capacity are formed. Further, a capacity with its one end connected to a constant potential source is formed between the gate electrode and the polycrystalline silicon electrode 106 by connecting the polycrystalline silicon electrode 106 to the fixed potential. A memory cell stable against external factors of alpha rays and others is thus obtainable.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP907080A JPS56107575A (en) | 1980-01-29 | 1980-01-29 | Manufacture of semicondutor device |
DE8181100607T DE3163340D1 (en) | 1980-01-29 | 1981-01-28 | Semiconductor device |
EP81100607A EP0033159B1 (en) | 1980-01-29 | 1981-01-28 | Semiconductor device |
US06/555,420 US4590508A (en) | 1980-01-29 | 1983-11-29 | MOS static ram with capacitively loaded gates to prevent alpha soft errors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP907080A JPS56107575A (en) | 1980-01-29 | 1980-01-29 | Manufacture of semicondutor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56107575A true JPS56107575A (en) | 1981-08-26 |
Family
ID=11710343
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP907080A Pending JPS56107575A (en) | 1980-01-29 | 1980-01-29 | Manufacture of semicondutor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56107575A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58155752A (en) * | 1982-03-12 | 1983-09-16 | Hitachi Ltd | Semiconductor memory storage |
JPS5923559A (en) * | 1982-07-30 | 1984-02-07 | Nec Corp | Semiconductor device |
JPS6028262A (en) * | 1983-07-26 | 1985-02-13 | Nec Corp | Semiconductor memory cell |
US4679171A (en) * | 1985-02-07 | 1987-07-07 | Visic, Inc. | MOS/CMOS memory cell |
JPH02150062A (en) * | 1988-11-30 | 1990-06-08 | Nec Corp | Cmos type static memory |
-
1980
- 1980-01-29 JP JP907080A patent/JPS56107575A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58155752A (en) * | 1982-03-12 | 1983-09-16 | Hitachi Ltd | Semiconductor memory storage |
JPS5923559A (en) * | 1982-07-30 | 1984-02-07 | Nec Corp | Semiconductor device |
JPS6028262A (en) * | 1983-07-26 | 1985-02-13 | Nec Corp | Semiconductor memory cell |
US4679171A (en) * | 1985-02-07 | 1987-07-07 | Visic, Inc. | MOS/CMOS memory cell |
JPH02150062A (en) * | 1988-11-30 | 1990-06-08 | Nec Corp | Cmos type static memory |
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