JPS5595338A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS5595338A
JPS5595338A JP241079A JP241079A JPS5595338A JP S5595338 A JPS5595338 A JP S5595338A JP 241079 A JP241079 A JP 241079A JP 241079 A JP241079 A JP 241079A JP S5595338 A JPS5595338 A JP S5595338A
Authority
JP
Japan
Prior art keywords
layer
sio
substrate
lead
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP241079A
Other languages
Japanese (ja)
Other versions
JPS5756216B2 (en
Inventor
Norio Matsui
Taichi Kon
Takaaki Osaki
Norio Nishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP241079A priority Critical patent/JPS5595338A/en
Publication of JPS5595338A publication Critical patent/JPS5595338A/en
Publication of JPS5756216B2 publication Critical patent/JPS5756216B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To provide multi-layer wiring on a chip by a method wherein multi-layer wiring is provided on an Si substrate, and etching is added to the back surface of the substrate to expose a wiring layer, then an IC chip is inserted into a hollow and connected to the layer by means of self-matching.
CONSTITUTION: An SiO2 film 201, an Al power source layer 301 of the pattern desired, an SiO2 layer 202 and an Al earthing layer 302 of the pattern desired are laminated on an Si substrate 1. Next an Al signal layer 303 provided with a lead portion 19, an SiO2 film 204 and an Al signal layer 304 are formed in such a manner that the lead 19 and the signal layer 304 are not piled up together on a concave portion 18. Then SiO2 205 and hydrofluoric acid resistant insulation film 131 are piled up. The Al layers are suitably connected each other in a longitudinal direction. An SiO2 mask 206 is provided on the under side of the substrate, and anisotropic etching is added to make a hollow 6. Then etching is added to the layer through the window 20 of the hollow to expose the lead 19, and an IC chip 5 with its electrode 8 located upward is inserted into the window. The lead 19 and the electrode are connected together using a laser beam through the transparent films 204, 205, then an Si substrate 11 for sealing it is attached 17.
COPYRIGHT: (C)1980,JPO&Japio
JP241079A 1979-01-12 1979-01-12 Integrated circuit Granted JPS5595338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP241079A JPS5595338A (en) 1979-01-12 1979-01-12 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP241079A JPS5595338A (en) 1979-01-12 1979-01-12 Integrated circuit

Publications (2)

Publication Number Publication Date
JPS5595338A true JPS5595338A (en) 1980-07-19
JPS5756216B2 JPS5756216B2 (en) 1982-11-29

Family

ID=11528469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP241079A Granted JPS5595338A (en) 1979-01-12 1979-01-12 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS5595338A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167936A (en) * 1984-09-11 1986-04-08 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS61292333A (en) * 1985-06-19 1986-12-23 Sumitomo Electric Ind Ltd Manufacture of semiconductor chip carrier
JP2002532876A (en) * 1998-12-07 2002-10-02 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Method for enclosing electronic components in a casing
JP2007214152A (en) * 2006-02-07 2007-08-23 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990001215A1 (en) * 1988-07-22 1990-02-08 Nippondenso Co., Ltd. Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167936A (en) * 1984-09-11 1986-04-08 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH0527984B2 (en) * 1984-09-11 1993-04-22 Mitsubishi Electric Corp
JPS61292333A (en) * 1985-06-19 1986-12-23 Sumitomo Electric Ind Ltd Manufacture of semiconductor chip carrier
JP2002532876A (en) * 1998-12-07 2002-10-02 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Method for enclosing electronic components in a casing
JP2007214152A (en) * 2006-02-07 2007-08-23 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP4637761B2 (en) * 2006-02-07 2011-02-23 パナソニック株式会社 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPS5756216B2 (en) 1982-11-29

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