JPS559488A - Method of making semiconductor device - Google Patents

Method of making semiconductor device

Info

Publication number
JPS559488A
JPS559488A JP8337678A JP8337678A JPS559488A JP S559488 A JPS559488 A JP S559488A JP 8337678 A JP8337678 A JP 8337678A JP 8337678 A JP8337678 A JP 8337678A JP S559488 A JPS559488 A JP S559488A
Authority
JP
Japan
Prior art keywords
layer
type
chip
header
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8337678A
Other languages
Japanese (ja)
Inventor
Tatsunori Nakajima
Kosei Kajiwara
Kosuke Yasuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8337678A priority Critical patent/JPS559488A/en
Publication of JPS559488A publication Critical patent/JPS559488A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To improve the characteristics such as low contact resistance by providing the silicon powder including the same conductivity type of impurities as that of a semiconductor chip between the chip and a header upon joining the chip with the header by a Au-Si eutectic technique.
CONSTITUTION: The epitaxial growth of a n-type layer 3 is first allowed to proceed on a p-type Si substrate 2 to isolate the layer 3 by a p-type region 2'; then p-type gate 4, n-type source 5 and drain region 6 are provided in the isolated region; and the back of the substrate 2 is etched to remove the high impurity content layer. Prior to joining the chip 1 made in this way with the header 7 conprising Kovar 8 and Au layer 9 coated thereon, the high concentration boron doped silicon powder 10 is coated on the layer 9. In this manner, boron segregates to provide a low electric resistance layer to the side of the substrate 2 resulting in low contact resistance.
COPYRIGHT: (C)1980,JPO&Japio
JP8337678A 1978-07-07 1978-07-07 Method of making semiconductor device Pending JPS559488A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8337678A JPS559488A (en) 1978-07-07 1978-07-07 Method of making semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8337678A JPS559488A (en) 1978-07-07 1978-07-07 Method of making semiconductor device

Publications (1)

Publication Number Publication Date
JPS559488A true JPS559488A (en) 1980-01-23

Family

ID=13800690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8337678A Pending JPS559488A (en) 1978-07-07 1978-07-07 Method of making semiconductor device

Country Status (1)

Country Link
JP (1) JPS559488A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013121794A1 (en) 2012-02-15 2013-08-22 Ｊｆｅ条鋼株式会社 Soft-nitriding steel and soft-nitrided component using steel as material

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4990879A (en) * 1972-12-28 1974-08-30

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4990879A (en) * 1972-12-28 1974-08-30

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013121794A1 (en) 2012-02-15 2013-08-22 Ｊｆｅ条鋼株式会社 Soft-nitriding steel and soft-nitrided component using steel as material

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