JPS5556662A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5556662A
JPS5556662A JP12853978A JP12853978A JPS5556662A JP S5556662 A JPS5556662 A JP S5556662A JP 12853978 A JP12853978 A JP 12853978A JP 12853978 A JP12853978 A JP 12853978A JP S5556662 A JPS5556662 A JP S5556662A
Authority
JP
Japan
Prior art keywords
constitution
channel region
share
layers
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12853978A
Other languages
Japanese (ja)
Inventor
Kunimitsu Fujiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP12853978A priority Critical patent/JPS5556662A/en
Publication of JPS5556662A publication Critical patent/JPS5556662A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To accomplish high-density integration by the constitution wherein three FET's share only one channel region commonly.
CONSTITUTION: An n+-layer 23 which is independent of n+-layers 21 and 22 is provided so that they become the source or drain of a FET around a channel region 60 in an Si-substrate surface covered with a gate-oxide film, and a conductive film 53 is provided in the same way as conductive films 51 and 52 are provided on the layers 21 and 22. In this constitution, an active element, wherein three NOSFET's (TR12,13,23) share only one channel region commonly, can be obtained, thereby the occupying area on the substrate is greatly reduced, and high-density integration can be accomplished.
COPYRIGHT: (C)1980,JPO&Japio
JP12853978A 1978-10-20 1978-10-20 Semiconductor device Pending JPS5556662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12853978A JPS5556662A (en) 1978-10-20 1978-10-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12853978A JPS5556662A (en) 1978-10-20 1978-10-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5556662A true JPS5556662A (en) 1980-04-25

Family

ID=14987248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12853978A Pending JPS5556662A (en) 1978-10-20 1978-10-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5556662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667217A (en) * 1985-04-19 1987-05-19 Ncr Corporation Two bit vertically/horizontally integrated memory cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667217A (en) * 1985-04-19 1987-05-19 Ncr Corporation Two bit vertically/horizontally integrated memory cell

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