JPS5552250A - Connecting structure in semiconductor integrated circuit - Google Patents
Connecting structure in semiconductor integrated circuitInfo
- Publication number
- JPS5552250A JPS5552250A JP12490978A JP12490978A JPS5552250A JP S5552250 A JPS5552250 A JP S5552250A JP 12490978 A JP12490978 A JP 12490978A JP 12490978 A JP12490978 A JP 12490978A JP S5552250 A JPS5552250 A JP S5552250A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- patch plate
- semiconductor integrated
- electrodes
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE: To provide a connecting structure in a semiconductor integrated circuit where the lead conection is made on the same level and, at the same time, shortened by a manner such that a semiconductor integrated circuit chip is placed in an area provided as depressed below the surface of a patch plate and both the semiconductor chip and the patch plate are connected through their respective electrodes by connecting leads at the same time in accordance with film carrier techiques.
CONSTITUTION: A patch plate 21 is provided with an area 22 depressed below the surface in which a semiconductor integrated circuit chip 23 is deposited, with its own electrodes and those of patch plate 21 being situated on an approximately same level. Each of the former electrodes has a metal bump 25 while each of the latter electrodes has a metal bump 24, the upper ends of these bumps being on the same level. The bumps 24 of the patch plate 21 and the bumps 25 of the semiconductor integrated circuit chip 23 are pressed with heat to be connected to each other at the same time by means of a plurality of connecting leads 27 provided on a film 26 of an organic insulator, such as polyamide. Thus the connected surface of the semiconductor chip and the patch plate is made identical, while each connecting lead 27 as set remains free from bending up- or downward, making it available to obtain fine connection in the shortest distance.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12490978A JPS5552250A (en) | 1978-10-11 | 1978-10-11 | Connecting structure in semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12490978A JPS5552250A (en) | 1978-10-11 | 1978-10-11 | Connecting structure in semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5552250A true JPS5552250A (en) | 1980-04-16 |
Family
ID=14897102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12490978A Pending JPS5552250A (en) | 1978-10-11 | 1978-10-11 | Connecting structure in semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5552250A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4860087A (en) * | 1986-03-26 | 1989-08-22 | Hitachi, Ltd. | Semiconductor device and process for producing the same |
US4907061A (en) * | 1986-10-08 | 1990-03-06 | Mitsubishi Denki Kabushiki Kaisha | Electronic device |
JPH02121343A (en) * | 1988-10-28 | 1990-05-09 | Ibiden Co Ltd | Film carrier |
JPH039973A (en) * | 1989-06-07 | 1991-01-17 | Shinko Electric Ind Co Ltd | Tape for tab and semiconductor device using it |
JPH05129507A (en) * | 1991-10-31 | 1993-05-25 | Hitachi Cable Ltd | Composite lead frame |
US5675684A (en) * | 1995-01-23 | 1997-10-07 | Hitachi, Ltd. | Optical module having semiconductor elements fixedly mounted thereon with improved accuracy |
-
1978
- 1978-10-11 JP JP12490978A patent/JPS5552250A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4860087A (en) * | 1986-03-26 | 1989-08-22 | Hitachi, Ltd. | Semiconductor device and process for producing the same |
US4907061A (en) * | 1986-10-08 | 1990-03-06 | Mitsubishi Denki Kabushiki Kaisha | Electronic device |
JPH02121343A (en) * | 1988-10-28 | 1990-05-09 | Ibiden Co Ltd | Film carrier |
JPH039973A (en) * | 1989-06-07 | 1991-01-17 | Shinko Electric Ind Co Ltd | Tape for tab and semiconductor device using it |
JPH05129507A (en) * | 1991-10-31 | 1993-05-25 | Hitachi Cable Ltd | Composite lead frame |
US5675684A (en) * | 1995-01-23 | 1997-10-07 | Hitachi, Ltd. | Optical module having semiconductor elements fixedly mounted thereon with improved accuracy |
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