JPH05129507A - Composite lead frame - Google Patents

Composite lead frame

Info

Publication number
JPH05129507A
JPH05129507A JP3286281A JP28628191A JPH05129507A JP H05129507 A JPH05129507 A JP H05129507A JP 3286281 A JP3286281 A JP 3286281A JP 28628191 A JP28628191 A JP 28628191A JP H05129507 A JPH05129507 A JP H05129507A
Authority
JP
Japan
Prior art keywords
lead frame
layer
copper
conductor
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3286281A
Other languages
Japanese (ja)
Other versions
JP2601079B2 (en
Inventor
Mamoru Onda
田 護 御
Masaharu Takagi
城 正 治 高
Kenji Yamaguchi
口 健 司 山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP3286281A priority Critical patent/JP2601079B2/en
Publication of JPH05129507A publication Critical patent/JPH05129507A/en
Application granted granted Critical
Publication of JP2601079B2 publication Critical patent/JP2601079B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item

Abstract

PURPOSE:To reduce the defect of a pattern by a method wherein, out of conductor layers on an insulating film layer, the conductor layers to be used as inside wiring layers are formed by sputtering or vapor-depositing copper or a copper alloy. CONSTITUTION:A lead frame 11 is provided with an outer frame 13. Outside wiring layers (outer leads) 15 (15a, 15b) are extended and installed toward parts near the center of the outer frame 13 from the outer frame 13. A flexible multilayer wiring board (FPC) 17 is arranged in the central part of the outer frame 13 of the lead frame 11. The FPC 17 is provided with inner wiring layers (inner leads) 27 on the upper side of an insulating film layer 19. The inner leads 27 are formed of a thin film by sputtering or vapor-depositing copper or a copper alloy. The inner leads 27 may be formed on both faces of the upper side and the lower side of the insulating film layer 19. Thereby, a defect such as a rolling flaw, a hole or the like is eliminated, and the defect of a pattern can be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、樹脂封止型の半導体装
置用の複合リードフレームに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated composite lead frame for semiconductor devices.

【0002】[0002]

【従来の技術】複合リードフレームの内側配線層となる
フレキシブル配線基板(以下、FPCという)は、従来
より銅箔にポリイミドを塗布して焼付けたキャスティン
グ材、またはポリイミドフィルムに銅箔を接着剤で貼付
けた材料が用いられている。前者はその構造から二層
材、後者は接着剤層を有するため三層材と呼称されてい
る。
2. Description of the Related Art A flexible wiring board (hereinafter referred to as FPC), which is an inner wiring layer of a composite lead frame, is conventionally a casting material obtained by coating a copper foil with polyimide and baking it, or a copper foil is bonded to a polyimide film with an adhesive. The pasted material is used. The former is called a two-layer material because of its structure, and the latter is called a three-layer material because it has an adhesive layer.

【0003】前記各材料は、銅箔の厚さの限界が後工程
での微細パターン形成時の各パターン寸法の限界となっ
ており、益々微細化の要求されてきた複合リードフレー
ムに対応出来なくなってきている。
In each of the above materials, the limit of the thickness of the copper foil is the limit of each pattern dimension at the time of forming a fine pattern in the subsequent process, and it becomes impossible to cope with the composite lead frame which is required to be further miniaturized. Is coming.

【0004】即ち、銅箔の製造可能限界厚さは現在18
μm であって図1に示すグラフから明らかなように、こ
の時の微細回路形成ピッチAは、必要な導体幅Cを90
μmとした場合に120μm が限界である。これはホト
レジストコートケミカルエッチングにおいて、パターン
間を溶解除去出来るスペースは銅箔厚さの約2倍までが
限界となっているためである。
That is, the limit thickness of copper foil that can be manufactured is currently 18
As is clear from the graph shown in FIG. 1, the fine circuit forming pitch A at this time has a required conductor width C of 90 μm.
The limit is 120 μm in terms of μm. This is because in the photoresist coating chemical etching, the space that can be dissolved and removed between the patterns is limited to about twice the thickness of the copper foil.

【0005】その原因はホトレジスト幅をいかにせまく
しても、銅箔が厚い場合は、エッチング時間が長くな
り、サイドエッチングが進むためである。なお、図1中
のBはパターン幅を示している。
The reason for this is that no matter how narrow the photoresist width is, if the copper foil is thick, the etching time becomes long and the side etching proceeds. In addition, B in FIG. 1 indicates a pattern width.

【0006】[0006]

【発明が解決しようとする課題】このため18μm 未満
の銅箔が必要となるが、実際には量産ベースでの連続圧
延法による製造は不可能である。
For this reason, a copper foil having a thickness of less than 18 μm is required, but in reality, it cannot be manufactured by a continuous rolling method on a mass production basis.

【0007】また、無電解銅めっき法によりポリイミド
に直接めっき膜を形成する方法も検討されているが、密
着性の良いめっき技術が未だ確立されていない。
Although a method of directly forming a plating film on polyimide by an electroless copper plating method has been studied, a plating technique with good adhesion has not been established yet.

【0008】本発明は、上記問題点を解消し、より微細
なパターンで、かつ高信頼性の複合リードフレームを提
供することを目的としている。
An object of the present invention is to solve the above problems and provide a composite lead frame having a finer pattern and high reliability.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に本発明の第1の態様によれば、絶縁フィルムの少なく
もと一方の面に導体層を有するフレキシブル配線基板
と、外側配線層となる金属導体とで構成してなる複合リ
ードフレームにおいて、前記導体層のうち、内側配線層
となる導体層を銅または銅合金のスパッタまたは蒸着に
より形成してなることを特徴とする複合リードフレーム
が提供される。
According to a first aspect of the present invention to achieve the above object, a flexible wiring board having a conductor layer on at least one side of an insulating film, and an outer wiring layer are provided. In the composite lead frame formed of the metal conductor, the composite lead frame is characterized in that, among the conductor layers, the conductor layer serving as an inner wiring layer is formed by sputtering or vapor deposition of copper or a copper alloy. Provided.

【0010】また、本発明の第2の態様によれば、前記
複合リードフレームの内側配線層となる導体層上に、さ
らに銅または銅合金めっき層を有することを特徴とする
複合リードフレームが提供される。
According to a second aspect of the present invention, there is provided a composite lead frame characterized by further comprising a copper or copper alloy plating layer on a conductor layer which is an inner wiring layer of the composite lead frame. To be done.

【0011】以下に本発明をさらに詳細に説明する。本
発明は、前記内側配線層となる導体層の形成がスパッタ
または蒸着による場合、1μm 厚さの形成は容易であ
り、この場合ホトレジストインクの解像度さえ高まれば
理論的には2μm のスペース形成も可能であるとの知見
によりなされたものである。
The present invention will be described in more detail below. According to the present invention, when the conductor layer serving as the inner wiring layer is formed by sputtering or vapor deposition, it is easy to form a 1 μm thick layer. In this case, a theoretically 2 μm space can be formed if the resolution of the photoresist ink is increased. It was made based on the knowledge that

【0012】図2は、本発明の一実施例を示す一部断面
説明図である。ところで、図面は、説明のために一部を
省略したり、簡略化してあり、実際のものとは異なるこ
とに注意されたい。
FIG. 2 is a partial cross sectional view showing an embodiment of the present invention. By the way, it should be noted that the drawings are partially omitted or simplified for the sake of explanation, and are different from actual ones.

【0013】リードフレーム11は外枠13を備え、こ
の外枠13から外側配線層であるアウターリード15
(15a,15b)が外枠13の中心近傍に向かって延
設されている。リードフレーム11の外枠13内の中心
部にはEPC17が配置される。このFPC17は、例
えばポリイミドよりなる絶縁フィルム層19の上側に内
側配線層となる導体層27を有する。前記導体層27は
銅または銅合金のスパッタまたは蒸着により薄膜に形成
される。
The lead frame 11 is provided with an outer frame 13, and from this outer frame 13, an outer lead 15 which is an outer wiring layer.
(15a, 15b) are extended toward the vicinity of the center of the outer frame 13. An EPC 17 is arranged in the center of the outer frame 13 of the lead frame 11. The FPC 17 has a conductor layer 27 serving as an inner wiring layer above the insulating film layer 19 made of, for example, polyimide. The conductor layer 27 is formed into a thin film by sputtering or vapor deposition of copper or a copper alloy.

【0014】この薄膜の導体層27は片面に限るもので
はなく絶縁フィルム層19の上側、下側の両面に形成し
てもよい。
The thin-film conductor layer 27 is not limited to one surface, but may be formed on both upper and lower surfaces of the insulating film layer 19.

【0015】この場合には、裏側にもパターンを切りス
ルーホール連結すると、接地層(最下層の張合せ層)を
含めて3層配線の複合フレームを作ることが出来る。
In this case, by cutting the pattern on the back side and connecting the through holes, it is possible to fabricate a composite frame of three-layer wiring including the ground layer (the lowest bonding layer).

【0016】この薄膜の導体層27は後に、例えば信号
層パターンが形成されて内側配線層であるインナーリー
ドとなる。絶縁フィルム層19は、接地および電源供給
用ホール23とロックホール25とがプレスパンチング
等により開口されており、さらにFPC17の四隅に切
り欠き29を設けている。この絶縁フィルム層19に導
体層21が接着剤等により貼着されている。このFPC
17の絶縁フィルム層19の少なくとも一方の面に形成
された薄膜の導体層を、エッチングまたは蒸着して、イ
ンナーリード27が形成されている。このインナーリー
ド27の内側先端には、ワイヤボンディング接続が良好
になされるように、例えばSn−Niの下地の上に金の
ような良導体がめっきされている。 前記FPC17の
ホール23にも、例えばSn−Niの下地の上に金のよ
うな良導体がめっきされている。前記リードフレーム1
1の外側配線層(アウターリード15)と、FPC17
の内側配線層(インナーリード27)との電気的接続
は、アウターリード15の先端に半田めっきを施した
後、アウターリード15とインナーリード27とを適切
に重複配置させ、それらを赤外線ビーム加熱法により加
熱圧着して達成されている。
This thin-film conductor layer 27 will later become an inner lead which is an inner wiring layer on which, for example, a signal layer pattern is formed. The insulating film layer 19 has holes 23 for grounding and power supply and a lock hole 25 opened by press punching or the like, and notches 29 are provided at four corners of the FPC 17. A conductor layer 21 is attached to the insulating film layer 19 with an adhesive or the like. This FPC
The inner lead 27 is formed by etching or vapor-depositing a thin-film conductor layer formed on at least one surface of the insulating film layer 19 of 17. At the inner tip of the inner lead 27, a good conductor such as gold is plated on the base of Sn-Ni, for example, in order to make a good wire bonding connection. The hole 23 of the FPC 17 is also plated with a good conductor such as gold on the base of Sn-Ni. The lead frame 1
1 outer wiring layer (outer lead 15) and the FPC 17
The electrical connection with the inner wiring layer (inner lead 27) is performed by solder-plating the tips of the outer leads 15 and then appropriately arranging the outer leads 15 and the inner leads 27 so that they are connected by the infrared beam heating method. It is achieved by thermocompression bonding.

【0017】ところで、この図において、リードフレー
ム11のアウターリード15は、外枠13の、例えば四
隅近傍からそれぞれ延在するリードを接地および電源供
給用リード15aとし、その他を信号用リード15bと
している。信号用リード15bは、上述したようにイン
ナーリード27との接続がなされているが、接地および
電源供給用リード15aは、導体層21に直接接地され
る。この接地のため、まず、上記絶縁フィルム層19の
切り欠き29から露出する導体層21の隅部に半田めっ
きによりバンプ31を形成し、このバンプ31に接地お
よび電源供給用リード15aの先端をあて、加熱圧着し
て、導体層21と接地および電源供給用リード15aと
を導通接続している。
In the figure, the outer leads 15 of the lead frame 11 are ground and power supply leads 15a extending from the outer frame 13 near, for example, four corners, and the other leads are signal leads 15b. .. The signal lead 15b is connected to the inner lead 27 as described above, but the ground and power supply lead 15a is directly grounded to the conductor layer 21. For this grounding, first, bumps 31 are formed by solder plating on the corners of the conductor layer 21 exposed from the notches 29 of the insulating film layer 19, and the tips of the grounding and power supply leads 15a are applied to the bumps 31. The conductor layer 21 is electrically connected to the ground and power supply lead 15a by thermocompression bonding.

【0018】かかる複合リードフレーム11に、半導体
素子33を搭載し、半導体素子33の信号端子とインナ
ーリード27のめっき端子との間をボンディングワイヤ
35でボンディング接続するとともに、さらに半導体素
子33の接地端子と導体層21のFPC17の接地およ
び電源供給用ホール23から露出する部分との間をボン
ディングワイヤ35でボンディングして接続する。 最
後にインナーリード27を包むように樹脂封止して半導
体装置を作製することができる。
The semiconductor element 33 is mounted on the composite lead frame 11, and the signal terminal of the semiconductor element 33 and the plating terminal of the inner lead 27 are connected by bonding wire 35, and the ground terminal of the semiconductor element 33 is further connected. The grounding of the FPC 17 of the conductor layer 21 and a portion exposed from the power supply hole 23 are connected by bonding with a bonding wire 35. Finally, a semiconductor device can be manufactured by resin-sealing so as to wrap the inner lead 27.

【0019】前記インナーリード27は、特に微細な配
線が要求されるものである。例えば、半導体素子33が
15mm角の場合インナーリードの微細化限界によって
多ピン化の限界も決まるため微細エッチングの技術開発
(エッチング液の組成等)が進められている。
The inner leads 27 are required to have particularly fine wiring. For example, when the semiconductor element 33 is 15 mm square, the limit of increasing the number of pins is determined by the limit of miniaturization of the inner lead, and therefore the technique development of fine etching (composition of etching solution etc.) is underway.

【0020】しかし、実際にはパターンの元となる導体
層材料の厚さによって自ら多ピン化の限界が決まって来
る。通常、銅箔18μm 厚さの場合には図1より15÷
0.12×4辺=500ピン配列が限界なのに対して、
例えば、3μm 厚さのスパッタまたは蒸着膜の場合には
15÷0.1×4=600ピンまで可能となる。また、
必要導体幅Cが90μm から、例えば70μm になるよ
うな場合には、さらに多ピン化が可能となる。
However, in reality, the limit of increasing the number of pins is determined by the thickness of the conductor layer material which is the source of the pattern. Normally, if the copper foil is 18 μm thick, it is 15 ÷ from Fig. 1.
0.12 × 4 sides = 500 pin arrangement is the limit,
For example, in the case of a 3 μm-thick sputter or vapor-deposited film, up to 15 / 0.1 × 4 = 600 pins are possible. Also,
When the required conductor width C is changed from 90 μm to, for example, 70 μm, the number of pins can be further increased.

【0021】例えば、3μm 厚さの純銅の導体薄膜をコ
ーティングしたポリイミドフィルムを作製する場合に
は、ポリイミドのコイルを連続蒸着設備に入れて純銅を
蒸発源として3μm の純銅薄膜をフィルムコイル全体に
形成させることができる。この場合に銅薄膜とポリイミ
ドとの密着性を向上させるためにポリイミドのフィルム
上をあらかじめプラズマ中で粗化しておくと良い。プラ
ズマ処理は、アルゴンイオンプラズマで0.01〜0.
2μm 程度の粗化が好ましい。
For example, in the case of producing a polyimide film coated with a conductor thin film of pure copper having a thickness of 3 μm, a polyimide coil is put in a continuous vapor deposition facility and pure copper thin film of 3 μm is formed on the entire film coil by using pure copper as an evaporation source. Can be made In this case, in order to improve the adhesion between the copper thin film and the polyimide, the polyimide film may be roughened in plasma in advance. The plasma treatment was performed with argon ion plasma in the range of 0.01 to 0.
A roughening of about 2 μm is preferable.

【0022】なお、前記銅薄膜の形成は蒸着に限るもの
ではなく、スパッタによっても良い。
The formation of the copper thin film is not limited to vapor deposition, but sputtering may be used.

【0023】この3μm 厚さの銅薄膜を保つフィルムを
多条切断して複合リードフレームの製造に用いることが
できる。この材料に所定のホール23、25等を施して
後、例えば接着剤により導体層21を貼合せる。その
後、インナーリード27をホトエッチング法により形成
し、さらにアウターリード15を連結して複合リードフ
レームとすることができる。
This film for holding a copper thin film having a thickness of 3 μm can be cut into multiple strips and used for the production of a composite lead frame. After forming predetermined holes 23, 25, etc. in this material, the conductor layer 21 is attached by, for example, an adhesive. After that, the inner leads 27 can be formed by the photoetching method, and the outer leads 15 can be further connected to form a composite lead frame.

【0024】また、本発明では、スパッタまたは蒸着に
より形成された薄膜の導体層上に、さらに銅または銅合
金めっき法によって厚付けする複合リードフレームも開
発した。即ち、電流容量の高いLSIでは3μm 程度の
銅の厚さが必要となるためである。前記めっき法は、電
気めっき、無電解めっきのいずれも用いることができ
る。
The present invention has also developed a composite lead frame in which a thin conductor layer formed by sputtering or vapor deposition is further thickened by a copper or copper alloy plating method. This is because an LSI having a high current capacity requires a copper thickness of about 3 μm. As the plating method, either electroplating or electroless plating can be used.

【0025】なお、上記導体層は銅または銅合金とした
が、銅合金としてはCu−Zn、Cu−Sn等の黄銅、
青銅を挙げることができる。
Although the conductor layer is made of copper or a copper alloy, the copper alloy may be brass such as Cu--Zn or Cu--Sn.
Bronze can be mentioned.

【0026】[0026]

【実施例】以下に本発明を実施例に基づき具体的に説明
する。 (実施例1)まず、インナーリード27の形成に3μm
の純銅の導体薄膜をコーティングしたポリイミドフィル
ムを用いた。ポリイミドの500mm幅で200mのコ
イルを連続蒸着設備に入れて純銅を蒸発源として3μm
の純銅薄膜をフィルムコイル全体に形成させた。
EXAMPLES The present invention will be specifically described below based on examples. (Example 1) First, the inner lead 27 is formed with a thickness of 3 μm.
A polyimide film coated with a conductor thin film of pure copper was used. Put a coil of polyimide of 500mm in width and 200m in continuous vapor deposition equipment and use pure copper as an evaporation source to 3μm
Of pure copper thin film was formed on the entire film coil.

【0027】この場合に銅薄膜とポリイミドの密着性を
向上させるためにポリイミドのフィルム上をあらかじめ
プラズマ中で粗化しておいた。プラズマ処理はアルゴン
イオンプラズマで0.07μm 程度に粗化した。
In this case, in order to improve the adhesion between the copper thin film and the polyimide, the polyimide film was preliminarily roughened in plasma. The plasma treatment was roughened to about 0.07 μm with argon ion plasma.

【0028】この3μm の銅薄膜を持つフィルムを70
mm幅に多条切断して複合リードフレームの製造に供し
た。この材料に所定のホール23,25等を開孔して
後、接着剤により導体層21を貼合せ、その後ホトエッ
チング法によりインナーリード27を形成した。さら
に、アウターリード15を連結して複合リードフレーム
とした。
The film having a copper thin film of 3 μm is 70
It was cut into multiple strips with a width of mm and used for manufacturing a composite lead frame. After forming predetermined holes 23, 25, etc. in this material, the conductor layer 21 was bonded with an adhesive, and then the inner lead 27 was formed by the photoetching method. Further, the outer leads 15 were connected to form a composite lead frame.

【0029】(実施例2)実施例1において薄膜の導体
層の形成方法として、まず、0.5μm の銅の蒸着膜を
作り、その上に電気めっき法により2.5μm の銅めっ
きを施して全体を3μm とした。この場合には蒸着膜は
電気が通る最低の膜厚で良いため高速の巻取蒸着が可能
となり生産性が向上した。
(Example 2) As a method of forming a thin-film conductor layer in Example 1, first, a vapor-deposited film of copper having a thickness of 0.5 μm was prepared, and then copper was plated with a thickness of 2.5 μm by electroplating. The entire size was 3 μm. In this case, since the vapor-deposited film may have a minimum thickness through which electricity can pass, high-speed roll-up vapor deposition is possible and productivity is improved.

【0030】実施例1、2ともピン数は600ピンであ
る。またアウターリード15の連結方法は、まずインナ
ーリード全体とボンディングホールおよび接地層が顔を
出している切欠き部29の低部に0.5〜1.0μm の
金めっきを施す。この金めっきは、ボンディングワイヤ
35のボンディング性能にすぐれるとともにAu−Sn
の共晶接合性にすぐれた金めっき種とした。
In both the first and second embodiments, the number of pins is 600. As for the method of connecting the outer leads 15, first, 0.5 to 1.0 .mu.m of gold plating is applied to the entire inner leads, the bonding hole, and the lower portion of the notch 29 where the ground layer is exposed. This gold plating is excellent in the bonding performance of the bonding wire 35 and is Au-Sn.
Was used as the gold plating seed with excellent eutectic bondability.

【0031】次に、アウターリードの先端に8〜10μ
m の純錫めっき31を施した。図ではバンプ31とした
が実際はバンプと言うほどの厚めっきでなくて良く8〜
10μm の先端めっきが最適である。この状態でFPC
とアウターリードとを一気に位置合せしてヒートコンタ
クトツール法により350〜400℃で5秒間加熱圧着
し接合して複合リードフレームとした。
Next, 8 to 10 μm is attached to the tip of the outer lead.
m of pure tin plating 31 was applied. In the figure, the bump 31 is used, but in actuality, it is not necessary to use thick plating such as a bump.
10 μm tip plating is optimal. FPC in this state
Then, the outer lead and the outer lead were aligned at a stretch, and they were heat-pressed at 350 to 400 ° C. for 5 seconds by the heat contact tool method to join them to obtain a composite lead frame.

【0032】実施例1、2の複合リードフレームは、い
ずれもインナーリードピッチが微細化でき、従来に比べ
1.5〜2.0倍の微細化率となった。
In each of the composite lead frames of Examples 1 and 2, the inner lead pitch could be miniaturized, and the miniaturization rate was 1.5 to 2.0 times that of the conventional one.

【0033】[0033]

【発明の効果】本発明は以上説明したように構成されて
いるので、インナーリードピッチを大幅に微細化でき
た。また、圧延きずや穴あき等の欠陥がなく、パターン
欠陥を少なくすることができた。また、欠陥が少ないた
め無欠陥のめっきをパターン上に形成することができ
た。
Since the present invention is constructed as described above, the inner lead pitch can be greatly reduced. Further, there were no defects such as rolling flaws and perforations, and pattern defects could be reduced. In addition, since there are few defects, defect-free plating could be formed on the pattern.

【図面の簡単な説明】[Brief description of drawings]

【図1】銅箔の厚さとFPCパターンのピッチおよび幅
との関係を示すグラフである。
FIG. 1 is a graph showing the relationship between the thickness of a copper foil and the pitch and width of an FPC pattern.

【図2】本発明の複合リードフレームの一実施例を説明
するための一部断面説明図である。
FIG. 2 is a partial cross-sectional explanatory view for explaining one embodiment of the composite lead frame of the present invention.

【図3】本発明の他の実施例を説明する断面図である。FIG. 3 is a sectional view illustrating another embodiment of the present invention.

【図4】本発明の他の実施例を説明する平面図である。FIG. 4 is a plan view illustrating another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11 リードフレーム 13 外枠 15 外側配線層(アウターリード) 17 フレキシブル多層配線基板 19 絶縁フィルム層 21 接地および電源供給用導体層 23 接地および電源供給用ホール 25 ロックホール 27 内側配線層(インナーリード) 29 切り欠き 31 バンプ 33 半導体素子 35 ボンデイングワイヤ 37 はんだ接合層 15a 接地および電源供給用リード 15b 信号用リード 11 Lead Frame 13 Outer Frame 15 Outer Wiring Layer (Outer Lead) 17 Flexible Multilayer Wiring Board 19 Insulating Film Layer 21 Grounding and Power Supply Conductor Layer 23 Grounding and Power Supply Hole 25 Lock Hole 27 Inner Wiring Layer (Inner Lead) 29 Notch 31 Bump 33 Semiconductor element 35 Bonding wire 37 Solder joint layer 15a Grounding and power supply lead 15b Signal lead

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁フィルムの少なくもと一方の面に導体
層を有するフレキシブル配線基板と、外側配線層となる
金属導体とで構成してなる複合リードフレームにおい
て、 前記導体層のうち、内側配線層となる導体層を銅または
銅合金のスパッタまたは蒸着により形成してなることを
特徴とする複合リードフレーム。
1. A composite lead frame comprising a flexible wiring board having a conductor layer on at least one surface of an insulating film and a metal conductor serving as an outer wiring layer, wherein inner wiring of the conductor layer is included. A composite lead frame, wherein a conductor layer to be a layer is formed by sputtering or vapor deposition of copper or a copper alloy.
【請求項2】請求項1に記載の複合リードフレームの内
側配線層となる導体層上に、さらに銅または銅合金めっ
き層を有することを特徴とする複合リードフレーム。
2. A composite lead frame according to claim 1, further comprising a copper or copper alloy plating layer on the conductor layer serving as an inner wiring layer of the composite lead frame.
JP3286281A 1991-10-31 1991-10-31 Composite lead frame Expired - Fee Related JP2601079B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3286281A JP2601079B2 (en) 1991-10-31 1991-10-31 Composite lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3286281A JP2601079B2 (en) 1991-10-31 1991-10-31 Composite lead frame

Publications (2)

Publication Number Publication Date
JPH05129507A true JPH05129507A (en) 1993-05-25
JP2601079B2 JP2601079B2 (en) 1997-04-16

Family

ID=17702338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3286281A Expired - Fee Related JP2601079B2 (en) 1991-10-31 1991-10-31 Composite lead frame

Country Status (1)

Country Link
JP (1) JP2601079B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552250A (en) * 1978-10-11 1980-04-16 Nippon Telegr & Teleph Corp <Ntt> Connecting structure in semiconductor integrated circuit
JPS62232948A (en) * 1986-04-03 1987-10-13 Sumitomo Metal Mining Co Ltd Lead frame
JPH01238151A (en) * 1988-03-18 1989-09-22 Nec Corp Lead frame for semiconductor device
JPH0384939A (en) * 1989-08-29 1991-04-10 Sumitomo Electric Ind Ltd Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552250A (en) * 1978-10-11 1980-04-16 Nippon Telegr & Teleph Corp <Ntt> Connecting structure in semiconductor integrated circuit
JPS62232948A (en) * 1986-04-03 1987-10-13 Sumitomo Metal Mining Co Ltd Lead frame
JPH01238151A (en) * 1988-03-18 1989-09-22 Nec Corp Lead frame for semiconductor device
JPH0384939A (en) * 1989-08-29 1991-04-10 Sumitomo Electric Ind Ltd Semiconductor device

Also Published As

Publication number Publication date
JP2601079B2 (en) 1997-04-16

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