JPS5544703A - Mos semiconductor device - Google Patents

Mos semiconductor device

Info

Publication number
JPS5544703A
JPS5544703A JP11655678A JP11655678A JPS5544703A JP S5544703 A JPS5544703 A JP S5544703A JP 11655678 A JP11655678 A JP 11655678A JP 11655678 A JP11655678 A JP 11655678A JP S5544703 A JPS5544703 A JP S5544703A
Authority
JP
Japan
Prior art keywords
film
gate
resistor
source
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11655678A
Other languages
Japanese (ja)
Inventor
Koji Nose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11655678A priority Critical patent/JPS5544703A/en
Publication of JPS5544703A publication Critical patent/JPS5544703A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE: To prevent charging of a gate during the manufacturing by forming an insulated resistor on a semiconductor substrate; connecting one end of the resistor to the gate of a dummy MOSFET; and by connecting the other end to the substrate, or the source on drain of a FET.
CONSTITUTION: A silicon oxide film 2, a drain-and source-diffused layer 3, and a polycrystal silicon film 4 which is to become a gate are formed on the surface of a semiconductor substrate 1 by a specified method, and a phosphorus glass film 5 for stabilizing the surface of the substrate 1 and for insulating layers of two-layer wirings is formed. Gate, drain, and source electrodes 6G, 6D, and 6S, and a surface-protecting film 7 made of a plasma-nitride film are formed on the film 5. A polycrystal silicon resistor 40 which is formed by the film 4 is provided in such a semiconductor device. One end of the resistor 40 is connected to the film 4 which becomes the gate 6G, and the extension thereof is snaked so as to obtain a specified resistance value. The other end of the resistor 40 is connected to an Al wiring 60 which is connected to the source 6S of the MOSFET, thereby charging of the gate during the manufacturing is prevented.
COPYRIGHT: (C)1980,JPO&Japio
JP11655678A 1978-09-25 1978-09-25 Mos semiconductor device Pending JPS5544703A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11655678A JPS5544703A (en) 1978-09-25 1978-09-25 Mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11655678A JPS5544703A (en) 1978-09-25 1978-09-25 Mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS5544703A true JPS5544703A (en) 1980-03-29

Family

ID=14690029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11655678A Pending JPS5544703A (en) 1978-09-25 1978-09-25 Mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5544703A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58187397A (en) * 1982-04-08 1983-11-01 ガオ・ゲゼルシヤフト・フユア・アウトマチオン・ウント・オルガニザチオン・ミツト・ベシユレンクテル・ハフツング Multilayer type identification card and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58187397A (en) * 1982-04-08 1983-11-01 ガオ・ゲゼルシヤフト・フユア・アウトマチオン・ウント・オルガニザチオン・ミツト・ベシユレンクテル・ハフツング Multilayer type identification card and its manufacture

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