JPS5541760A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5541760A
JPS5541760A JP11534278A JP11534278A JPS5541760A JP S5541760 A JPS5541760 A JP S5541760A JP 11534278 A JP11534278 A JP 11534278A JP 11534278 A JP11534278 A JP 11534278A JP S5541760 A JPS5541760 A JP S5541760A
Authority
JP
Japan
Prior art keywords
recess
leads
center
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11534278A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6231498B2 (enExample
Inventor
Katsuhiko Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11534278A priority Critical patent/JPS5541760A/ja
Publication of JPS5541760A publication Critical patent/JPS5541760A/ja
Publication of JPS6231498B2 publication Critical patent/JPS6231498B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP11534278A 1978-09-19 1978-09-19 Semiconductor device Granted JPS5541760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11534278A JPS5541760A (en) 1978-09-19 1978-09-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11534278A JPS5541760A (en) 1978-09-19 1978-09-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5541760A true JPS5541760A (en) 1980-03-24
JPS6231498B2 JPS6231498B2 (enExample) 1987-07-08

Family

ID=14660160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11534278A Granted JPS5541760A (en) 1978-09-19 1978-09-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5541760A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6047699A (ja) * 1983-08-26 1985-03-15 久保田　煕 果糖の分離法
US4989068A (en) * 1988-02-12 1991-01-29 Hitachi, Ltd. Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6047699A (ja) * 1983-08-26 1985-03-15 久保田　煕 果糖の分離法
US4989068A (en) * 1988-02-12 1991-01-29 Hitachi, Ltd. Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JPS6231498B2 (enExample) 1987-07-08

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