JPS54152867A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS54152867A
JPS54152867A JP6106378A JP6106378A JPS54152867A JP S54152867 A JPS54152867 A JP S54152867A JP 6106378 A JP6106378 A JP 6106378A JP 6106378 A JP6106378 A JP 6106378A JP S54152867 A JPS54152867 A JP S54152867A
Authority
JP
Japan
Prior art keywords
tab
lead
solder
lead frame
coat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6106378A
Other languages
Japanese (ja)
Other versions
JPS624860B2 (en
Inventor
Tomio Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6106378A priority Critical patent/JPS54152867A/en
Publication of JPS54152867A publication Critical patent/JPS54152867A/en
Publication of JPS624860B2 publication Critical patent/JPS624860B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the cost as well as to increase the life time of the semiconductor device by convering via the solder coat all over the tab to which the circuit element is attached and the surface of the lead frame containing plural leads to be the external terminals and enclosing the tab. CONSTITUTION:Tab 2 to which circuit element 1 is attached is composed of the laminated layer in which Ti, Ni and Ag are laminated from the lower part, and the entire surface of the tab is covered with solder coat 4. At the same time, the surface of lead frame 5 containing plural leads 3 enclosing tab 2 is also convered with coat 4, and element 1 is stuck onto tab 2 with the electrode provided to element 1 connected to frame 5 via wire 6. After this, element 1, wire 6 and the inner edge part of lead 3 are molded with resin 7, and the undesired lead 3 is cut off. And lead 3 protruded outside is bent to secure the dual-line type. Thus, the solder featuring a high solderbility is used and with no use of Au, Ag and the like.
JP6106378A 1978-05-24 1978-05-24 Lead frame Granted JPS54152867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6106378A JPS54152867A (en) 1978-05-24 1978-05-24 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6106378A JPS54152867A (en) 1978-05-24 1978-05-24 Lead frame

Publications (2)

Publication Number Publication Date
JPS54152867A true JPS54152867A (en) 1979-12-01
JPS624860B2 JPS624860B2 (en) 1987-02-02

Family

ID=13160322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6106378A Granted JPS54152867A (en) 1978-05-24 1978-05-24 Lead frame

Country Status (1)

Country Link
JP (1) JPS54152867A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920074A (en) * 1987-02-25 1990-04-24 Hitachi, Ltd. Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof
US5889317A (en) * 1997-04-09 1999-03-30 Sitron Precision Co., Ltd. Leadframe for integrated circuit package
US6896976B2 (en) * 2003-04-09 2005-05-24 International Rectifier Corporation Tin antimony solder for MOSFET with TiNiAg back metal

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02209622A (en) * 1989-02-03 1990-08-21 Nippon Seiko Kk Static pressure pneumatic bearing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920074A (en) * 1987-02-25 1990-04-24 Hitachi, Ltd. Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof
US5889317A (en) * 1997-04-09 1999-03-30 Sitron Precision Co., Ltd. Leadframe for integrated circuit package
US6896976B2 (en) * 2003-04-09 2005-05-24 International Rectifier Corporation Tin antimony solder for MOSFET with TiNiAg back metal

Also Published As

Publication number Publication date
JPS624860B2 (en) 1987-02-02

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