JPS55166941A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS55166941A
JPS55166941A JP7438279A JP7438279A JPS55166941A JP S55166941 A JPS55166941 A JP S55166941A JP 7438279 A JP7438279 A JP 7438279A JP 7438279 A JP7438279 A JP 7438279A JP S55166941 A JPS55166941 A JP S55166941A
Authority
JP
Japan
Prior art keywords
electrodes
cover
substrate
lead wires
external lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7438279A
Other languages
Japanese (ja)
Inventor
Takemi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7438279A priority Critical patent/JPS55166941A/en
Publication of JPS55166941A publication Critical patent/JPS55166941A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To eliminate the connection of lead wires for a semiconductor device and reduce the inductance of the lead wire by raising the electrodes of a high frequency semiconductor element and sealing the cover of a container having external lead wires connected to the raised electrodes. CONSTITUTION:Base and emitter electrodes 2 and 3 are raised with Au, Ag, etc. on a semiconductor chip 1 such as a transistor or the like. The chip 1 is fixed onto a metallized surface 6 formed on the surface of a ceramic substrate 5. An electrode 7 connected to the metallized surface 6 is provided via a through hole on the lower surface of the substrate 5. Base and emitter external lead wires 2a and 3a are provided on the outer surface of a cover 8 of recessed ceramic, and contact metals 2b, 3b connected through hole thereto are provided on the inner surface. The cover and the substrate are sealed with adhesive 9. In this manner, it eliminates the connection between the external lead wire and the electrodes so as to improve the high frequency characteristics.
JP7438279A 1979-06-13 1979-06-13 Semiconductor device Pending JPS55166941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7438279A JPS55166941A (en) 1979-06-13 1979-06-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7438279A JPS55166941A (en) 1979-06-13 1979-06-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS55166941A true JPS55166941A (en) 1980-12-26

Family

ID=13545553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7438279A Pending JPS55166941A (en) 1979-06-13 1979-06-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55166941A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0235503A2 (en) * 1986-02-24 1987-09-09 Hewlett-Packard Company hermetic high frequency surface mount microelectronic package
US4839717A (en) * 1986-12-19 1989-06-13 Fairchild Semiconductor Corporation Ceramic package for high frequency semiconductor devices
FR2629271A1 (en) * 1988-03-25 1989-09-29 Thomson Hybrides Microondes DEVICE FOR INTERCONNECTING AND PROTECTING A BULK MICROFREQUENCY COMPONENT BLEACH
EP0764393A4 (en) * 1995-03-02 1997-05-07
JP2005506701A (en) * 2001-10-17 2005-03-03 ハイマイト アクティーゼルスカブ Semiconductor structure with one or more through holes
JP2006041532A (en) * 2004-07-27 2006-02-09 Samsung Electronics Co Ltd Cap wafer having hollow part, semiconductor package using same, and manufacturing method of cap wafer

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0235503A2 (en) * 1986-02-24 1987-09-09 Hewlett-Packard Company hermetic high frequency surface mount microelectronic package
US4839717A (en) * 1986-12-19 1989-06-13 Fairchild Semiconductor Corporation Ceramic package for high frequency semiconductor devices
FR2629271A1 (en) * 1988-03-25 1989-09-29 Thomson Hybrides Microondes DEVICE FOR INTERCONNECTING AND PROTECTING A BULK MICROFREQUENCY COMPONENT BLEACH
US4996588A (en) * 1988-03-25 1991-02-26 Thomson Hybrides Et Microondes Device for interconnection and protection of a bare microwave component chip
EP0764393A4 (en) * 1995-03-02 1997-05-07
US5832598A (en) * 1995-03-02 1998-11-10 Circuit Components Incorporated Method of making microwave circuit package
JP2005506701A (en) * 2001-10-17 2005-03-03 ハイマイト アクティーゼルスカブ Semiconductor structure with one or more through holes
JP2006041532A (en) * 2004-07-27 2006-02-09 Samsung Electronics Co Ltd Cap wafer having hollow part, semiconductor package using same, and manufacturing method of cap wafer
JP4732824B2 (en) * 2004-07-27 2011-07-27 三星電子株式会社 Cap wafer with cavity, semiconductor package using the same, and cap wafer manufacturing method

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