JPS55148450A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS55148450A
JPS55148450A JP5553779A JP5553779A JPS55148450A JP S55148450 A JPS55148450 A JP S55148450A JP 5553779 A JP5553779 A JP 5553779A JP 5553779 A JP5553779 A JP 5553779A JP S55148450 A JPS55148450 A JP S55148450A
Authority
JP
Japan
Prior art keywords
metallized
input terminal
transistor chip
input
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5553779A
Other languages
Japanese (ja)
Other versions
JPS6249988B2 (en
Inventor
Yoshiaki Matsumae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5553779A priority Critical patent/JPS55148450A/en
Publication of JPS55148450A publication Critical patent/JPS55148450A/en
Publication of JPS6249988B2 publication Critical patent/JPS6249988B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To eliminate the necessity of a bridge in a semiconductor device and minimize the interval between an input terminal metallized and a chip by containing a transistor chip in the vicinity of the center thereof and disposing a ground metallized and a through hole at the output side. CONSTITUTION:Emitter ground metallized 5 is formed at an output side 12. An input terminal base metallized 8 is carried on an output terminal collector metallized 3 with a transistor chip 1 to be approached thereto. Since the length of the input terminal connecting bonding wire 9 can be therefore shortened, the operation Q factor at the input side formed of the input impedance of the bonding wire 9 and the transistor chip 1 can be lowered.
JP5553779A 1979-05-07 1979-05-07 Semiconductor device Granted JPS55148450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5553779A JPS55148450A (en) 1979-05-07 1979-05-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5553779A JPS55148450A (en) 1979-05-07 1979-05-07 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS55148450A true JPS55148450A (en) 1980-11-19
JPS6249988B2 JPS6249988B2 (en) 1987-10-22

Family

ID=13001464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5553779A Granted JPS55148450A (en) 1979-05-07 1979-05-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55148450A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132149A (en) * 1983-01-17 1984-07-30 Mitsubishi Electric Corp Ultrahigh frequency transistor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6355889U (en) * 1986-09-29 1988-04-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132149A (en) * 1983-01-17 1984-07-30 Mitsubishi Electric Corp Ultrahigh frequency transistor device

Also Published As

Publication number Publication date
JPS6249988B2 (en) 1987-10-22

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