JPS5797661A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5797661A
JPS5797661A JP55176032A JP17603280A JPS5797661A JP S5797661 A JPS5797661 A JP S5797661A JP 55176032 A JP55176032 A JP 55176032A JP 17603280 A JP17603280 A JP 17603280A JP S5797661 A JPS5797661 A JP S5797661A
Authority
JP
Japan
Prior art keywords
conductor
chips
common
terminal
emitters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55176032A
Other languages
Japanese (ja)
Other versions
JPS6230701B2 (en
Inventor
Yoshitaka Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55176032A priority Critical patent/JPS5797661A/en
Publication of JPS5797661A publication Critical patent/JPS5797661A/en
Publication of JPS6230701B2 publication Critical patent/JPS6230701B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6644Packaging aspects of high-frequency amplifiers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To prevent uneven current due to parasitic inductance by providing conductor wiring, connecting to a main electrode of each chip, which is doubled back parallel in a device provided on a substrate having a plurality of semiconductor element chips in parallel connection. CONSTITUTION:Transistor chips 1a, 1b are made on a substrate 7 and collectors of the chips are connected to a common collector terminal 2 and the emitters to the common emitter terminal 3 and the bases to the common base terminal 4. The emitters of the chips 1a, 1b and the common emitter terminal 3 are connected by the emitter connecting conductor 5 and a doubling back conductor 9 that makes u shap with the conductor 5. The currents that flow in the conductor 5 and the conductor 9 are opposite in directions which offset parasitic inductance making the same amount of current flows in the chips 1a and 1b.
JP55176032A 1980-12-10 1980-12-10 Semiconductor device Granted JPS5797661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55176032A JPS5797661A (en) 1980-12-10 1980-12-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55176032A JPS5797661A (en) 1980-12-10 1980-12-10 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5797661A true JPS5797661A (en) 1982-06-17
JPS6230701B2 JPS6230701B2 (en) 1987-07-03

Family

ID=16006527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55176032A Granted JPS5797661A (en) 1980-12-10 1980-12-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5797661A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984457A (en) * 1982-11-04 1984-05-16 Mitsubishi Electric Corp Gate turn off thyristor
JPS62103265U (en) * 1985-12-19 1987-07-01
JPS63193553A (en) * 1987-01-21 1988-08-10 シーメンス、アクチエンゲゼルシヤフト Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984457A (en) * 1982-11-04 1984-05-16 Mitsubishi Electric Corp Gate turn off thyristor
JPS62103265U (en) * 1985-12-19 1987-07-01
JPH0747872Y2 (en) * 1985-12-19 1995-11-01 富士電機株式会社 Semiconductor device
JPS63193553A (en) * 1987-01-21 1988-08-10 シーメンス、アクチエンゲゼルシヤフト Semiconductor device
US4907068A (en) * 1987-01-21 1990-03-06 Siemens Aktiengesellschaft Semiconductor arrangement having at least one semiconductor body

Also Published As

Publication number Publication date
JPS6230701B2 (en) 1987-07-03

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