JPS55128848A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS55128848A
JPS55128848A JP3600679A JP3600679A JPS55128848A JP S55128848 A JPS55128848 A JP S55128848A JP 3600679 A JP3600679 A JP 3600679A JP 3600679 A JP3600679 A JP 3600679A JP S55128848 A JPS55128848 A JP S55128848A
Authority
JP
Japan
Prior art keywords
chip
electrode
collector
base
metallized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3600679A
Other languages
Japanese (ja)
Other versions
JPS6257105B2 (en
Inventor
Keiichi Hirai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3600679A priority Critical patent/JPS55128848A/en
Publication of JPS55128848A publication Critical patent/JPS55128848A/en
Publication of JPS6257105B2 publication Critical patent/JPS6257105B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To protect a semiconductor chip against a damage even if the chip is turned over during fabrication by bending the end of a lead electrode formed on a substrate in L shape and projecting it upwardly when connecting the electrode to the chip upon carrying of the chip on an insulating substrate. CONSTITUTION:A transistor element 1 is soldered onto a collector electrode land 21 metallized on the surface of a thermocondictive insulating substrate 2 formed with a metal 24 on the side surface and with a metallized layer 25 on the back surface. Lead electrodes 31, 33 are also soldered to collector and base electrode lands 21, 22, respectively metallized to the substrate 2, and the electrodes of the element 1 are connected to the base and emitter electrode lands 22, 23, respectively using bonding wires 41, 42, respectively. In this configuration the ends of the collector and base lead electrodes 31, 33 are bent upwardly in L shape to produce projections 32, 34, respectively. Thus, even if the element is turned over, the element and the wires are not damaged.
JP3600679A 1979-03-27 1979-03-27 Semiconductor device Granted JPS55128848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3600679A JPS55128848A (en) 1979-03-27 1979-03-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3600679A JPS55128848A (en) 1979-03-27 1979-03-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS55128848A true JPS55128848A (en) 1980-10-06
JPS6257105B2 JPS6257105B2 (en) 1987-11-30

Family

ID=12457676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3600679A Granted JPS55128848A (en) 1979-03-27 1979-03-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55128848A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115851A (en) * 1981-01-10 1982-07-19 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115851A (en) * 1981-01-10 1982-07-19 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPS6257105B2 (en) 1987-11-30

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