JPS5527617A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method

Info

Publication number
JPS5527617A
JPS5527617A JP10055678A JP10055678A JPS5527617A JP S5527617 A JPS5527617 A JP S5527617A JP 10055678 A JP10055678 A JP 10055678A JP 10055678 A JP10055678 A JP 10055678A JP S5527617 A JPS5527617 A JP S5527617A
Authority
JP
Japan
Prior art keywords
type
film
region
base
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10055678A
Other languages
Japanese (ja)
Inventor
Hiroshi Saikai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10055678A priority Critical patent/JPS5527617A/en
Publication of JPS5527617A publication Critical patent/JPS5527617A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To easily realize low-power consumption and high-speed IIL by providing a gradient for the impurity concentration of the base region of a horizontal-type transistor Tr from the neighborhood of the emitter so as to facilitate the carrier diffusion. CONSTITUTION:N-type semiconductor layer 2 is grown on N<+>-type base, and its surface is covered with Si oxide film 15 and Si nitride film 16. Windows 17 and 18 are formed on the region where emitter 3 and collector 4 of a horizontal type PNP Tr are to be formed by removing films 15 and 16. Then, Si oxide film 19 is formed and window 20 is provided. By this, P is diffused and base 13 of high N<+> concentration is formed. On top of this, film 19 is grown. Next, by removing film 19, P-type impurity is introduced from windows 17 and 18, and thereby No.1 and No.2 N<+>-type regions 3 and 4 are formed. Then, by selective diffusion, No.1 and No.2 N<+>-type regions 3 and 4 are formed inside No.2 P-type region, and then power source terminal 7, input terminal 8 and No.1 and No.2 output terminals 9 and 10 are provided.
JP10055678A 1978-08-17 1978-08-17 Semiconductor device manufacturing method Pending JPS5527617A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10055678A JPS5527617A (en) 1978-08-17 1978-08-17 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10055678A JPS5527617A (en) 1978-08-17 1978-08-17 Semiconductor device manufacturing method

Publications (1)

Publication Number Publication Date
JPS5527617A true JPS5527617A (en) 1980-02-27

Family

ID=14277200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10055678A Pending JPS5527617A (en) 1978-08-17 1978-08-17 Semiconductor device manufacturing method

Country Status (1)

Country Link
JP (1) JPS5527617A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6464353A (en) * 1987-06-11 1989-03-10 Fairchild Semiconductor Manufacture of self-aligning high performance lateral operation silicon control rectfier and static ram

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS517884A (en) * 1974-07-09 1976-01-22 Tokyo Shibaura Electric Co
JPS5160478A (en) * 1974-11-22 1976-05-26 Mitsubishi Electric Corp

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS517884A (en) * 1974-07-09 1976-01-22 Tokyo Shibaura Electric Co
JPS5160478A (en) * 1974-11-22 1976-05-26 Mitsubishi Electric Corp

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6464353A (en) * 1987-06-11 1989-03-10 Fairchild Semiconductor Manufacture of self-aligning high performance lateral operation silicon control rectfier and static ram

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