JPS5522889A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5522889A
JPS5522889A JP5223779A JP5223779A JPS5522889A JP S5522889 A JPS5522889 A JP S5522889A JP 5223779 A JP5223779 A JP 5223779A JP 5223779 A JP5223779 A JP 5223779A JP S5522889 A JPS5522889 A JP S5522889A
Authority
JP
Japan
Prior art keywords
possibility
resin sealing
good soldering
covered
tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5223779A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5631896B2 (fa
Inventor
Tomoaki Kojima
Tomoichi Oku
Hitoshi Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5223779A priority Critical patent/JPS5522889A/ja
Publication of JPS5522889A publication Critical patent/JPS5522889A/ja
Publication of JPS5631896B2 publication Critical patent/JPS5631896B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP5223779A 1979-04-27 1979-04-27 Manufacturing method of semiconductor device Granted JPS5522889A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5223779A JPS5522889A (en) 1979-04-27 1979-04-27 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5223779A JPS5522889A (en) 1979-04-27 1979-04-27 Manufacturing method of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP11670274A Division JPS5329549B2 (fa) 1974-10-09 1974-10-09

Publications (2)

Publication Number Publication Date
JPS5522889A true JPS5522889A (en) 1980-02-18
JPS5631896B2 JPS5631896B2 (fa) 1981-07-24

Family

ID=12909106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5223779A Granted JPS5522889A (en) 1979-04-27 1979-04-27 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5522889A (fa)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034350A (en) * 1987-09-23 1991-07-23 Sgs Thomson Microelectronics S.R.L. Semiconductor device package with dies mounted on both sides of the central pad of a metal frame

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57199096U (fa) * 1981-06-10 1982-12-17
JPS6083096U (ja) * 1983-11-10 1985-06-08 株式会社サンエツ 浮遊物の除去装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4826074A (fa) * 1971-08-04 1973-04-05
JPS499912A (fa) * 1972-05-13 1974-01-29
JPS4924775A (fa) * 1972-06-26 1974-03-05

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4826074A (fa) * 1971-08-04 1973-04-05
JPS499912A (fa) * 1972-05-13 1974-01-29
JPS4924775A (fa) * 1972-06-26 1974-03-05

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034350A (en) * 1987-09-23 1991-07-23 Sgs Thomson Microelectronics S.R.L. Semiconductor device package with dies mounted on both sides of the central pad of a metal frame

Also Published As

Publication number Publication date
JPS5631896B2 (fa) 1981-07-24

Similar Documents

Publication Publication Date Title
IE822564L (en) Fabrication a semiconductor device having a phosphosilicate glass layer
JPS56122156A (en) Lead frame for semiconductor device
JPS5522889A (en) Manufacturing method of semiconductor device
JPS5764953A (en) Semiconductor device
JPS57139952A (en) Resin sealing type semiconductor device
JPS57154863A (en) Manufacture of resin sealing type electronic parts
JPS56158462A (en) Lead frame for single inline semiconductor device
JPS5740986A (en) Light-emitting element
JPS5629355A (en) Manufacture of resin-sealed semiconductor device
JPS572537A (en) Semiconductor device
JPS56103454A (en) Slaglead
JPS5735354A (en) Sealing method for semiconductor housing container
JPS56122155A (en) Lead frame for semiconductor device
JPS6412560A (en) Semiconductor device
JPS55162247A (en) Composite ic device
JPS6318652A (ja) 半導体装置の製造方法
JPS6427236A (en) Wire bonding method
JPS6435921A (en) Manufacture of semiconductor device
JPS57128947A (en) Semiconductor device
JPS57211759A (en) Electronic parts and manufacture thereof
JPS57167664A (en) Lead-out structure of lead wire in polymer film package
JPS5745964A (en) Manufacture of hybrid integrated circuit
JPS57201053A (en) Sealing method for semiconductor device
JPS5567155A (en) Preparation of semiconductor device
JPS57172757A (en) Manufacture of semiconductor device