JPS5745964A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS5745964A
JPS5745964A JP55122052A JP12205280A JPS5745964A JP S5745964 A JPS5745964 A JP S5745964A JP 55122052 A JP55122052 A JP 55122052A JP 12205280 A JP12205280 A JP 12205280A JP S5745964 A JPS5745964 A JP S5745964A
Authority
JP
Japan
Prior art keywords
leads
frame
integrated circuit
hybrid integrated
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55122052A
Other languages
Japanese (ja)
Inventor
Eiji Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55122052A priority Critical patent/JPS5745964A/en
Publication of JPS5745964A publication Critical patent/JPS5745964A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce by half the connecting portions of a hybrid integrated circuit by forming leads for external terminal of a frame and connecting the leads for the external terminal directly to the electrodes of an IC substrate without using wires nor lead wires. CONSTITUTION:A frame 1 has leads 8 for external terminal, the leads 8 are pressed to be reduced in thickness, are then bent to be brought into the position of the respective electrodes 5 of an IC as a connecting part. The leads 8 are disposed at a frame 1 corresponding to the electrodes 5 of the IC. When the frame 1 is bonded at 3 to a substrate 2, the connecting part 10 of the leads 8 is positioned at the respective electrodes 5, and is thereafter soldered at 6 to complete it. With this configuration, the molten part is reduced by half from the conventional one, and an IC of inexpensive cost and high reliability can be obtained.
JP55122052A 1980-09-02 1980-09-02 Manufacture of hybrid integrated circuit Pending JPS5745964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55122052A JPS5745964A (en) 1980-09-02 1980-09-02 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55122052A JPS5745964A (en) 1980-09-02 1980-09-02 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5745964A true JPS5745964A (en) 1982-03-16

Family

ID=14826417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55122052A Pending JPS5745964A (en) 1980-09-02 1980-09-02 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5745964A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0077276A2 (en) * 1981-10-13 1983-04-20 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Method for fabricating a hybrid circuit module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0077276A2 (en) * 1981-10-13 1983-04-20 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Method for fabricating a hybrid circuit module
EP0077276A3 (en) * 1981-10-13 1986-03-26 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Method for fabricating a hybrid circuit module

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