JPS55128844A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS55128844A
JPS55128844A JP3508479A JP3508479A JPS55128844A JP S55128844 A JPS55128844 A JP S55128844A JP 3508479 A JP3508479 A JP 3508479A JP 3508479 A JP3508479 A JP 3508479A JP S55128844 A JPS55128844 A JP S55128844A
Authority
JP
Japan
Prior art keywords
groove
substrate
film
exposed
mesa
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3508479A
Other languages
Japanese (ja)
Inventor
Fumio Tobioka
Hidekatsu Ito
Kenji Azetsubo
Shigefumi Kadowaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3508479A priority Critical patent/JPS55128844A/en
Publication of JPS55128844A publication Critical patent/JPS55128844A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: To form a flat surface of a semiconductor device by forming an oxide film having wider opening than the width of a mesa groove formed later on a semiconductor substrate formed with a pn junction, and coating a glass layer including the surface of the substrate exposed on both sides of the groove after perforating the groove.
CONSTITUTION: A SiO2 film 12 is coated on the surface of a silicon substrate 11 formed with emitter region, base region, etc., and a wider opening 12 than the width of a mesa groove 15 is performed at the film 12 at the position corresponding to the groove 15. With a photoresist film 14 as a mask the film 12 is etched to form a mesa groove 15 through the pn junction, the film 14 is then removed, and the surface 16 of the substrate 11 is exposed at the peripheral edge of the groove 15. Thereafter, glass powder 15 is filled in the groove 15 by an electrophoresis, simultaneously spread on the exposed surface 16 of the substrate 11 in a sufficient thickness. It is then calcined to form a glass passivation film 18 in silightly reduced volume. Thus, the surface of the substrate may be flat. Accordingly, no stepwise disconnection occurs at the wire of the electrode on the substrate.
COPYRIGHT: (C)1980,JPO&Japio
JP3508479A 1979-03-27 1979-03-27 Semiconductor device Pending JPS55128844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3508479A JPS55128844A (en) 1979-03-27 1979-03-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3508479A JPS55128844A (en) 1979-03-27 1979-03-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS55128844A true JPS55128844A (en) 1980-10-06

Family

ID=12432096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3508479A Pending JPS55128844A (en) 1979-03-27 1979-03-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55128844A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108771A (en) * 1977-03-04 1978-09-21 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108771A (en) * 1977-03-04 1978-09-21 Nec Corp Semiconductor device

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