JPS54148481A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54148481A
JPS54148481A JP5657178A JP5657178A JPS54148481A JP S54148481 A JPS54148481 A JP S54148481A JP 5657178 A JP5657178 A JP 5657178A JP 5657178 A JP5657178 A JP 5657178A JP S54148481 A JPS54148481 A JP S54148481A
Authority
JP
Japan
Prior art keywords
film
sio
layer
coated
psg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5657178A
Other languages
Japanese (ja)
Inventor
Seiichi Takahashi
Katsuzo Uenishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP5657178A priority Critical patent/JPS54148481A/en
Publication of JPS54148481A publication Critical patent/JPS54148481A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: To avoid the electric deterioration of the PN junction by limiting formation of the PSG film functioning as the 1st protective film of a high etching speed only on the N-type layer and avoiding etching the PSG film when the contact hole is formed.
CONSTITUTION: P+-type layer 1a is formed by diffusion on the surface of wafer 1 the N-type layer of which is epitaxial-grown on N+-type Si substrate, and then the entire surface of the wafer is covered with SiO2 film 2. An opening is drilled to dilm 2, and Si3N4 film 4a is coated over remaining film 2. Using film 4a as the mask, the mesa etching is applied to layer 1a and the epitaxial layer. And SiO2 film 2c protects the mesa-etched area. After this, PSG film 3 is coated only on the surface of film 2c plus coating of SiO2 film 4b. The contact hole is drilled to film 4a via the photolithography method. In such way, the hole is formed while film 3 is protected with film 4b, and electrode metal 5 is coated to the hole.
COPYRIGHT: (C)1979,JPO&Japio
JP5657178A 1978-05-15 1978-05-15 Manufacture of semiconductor device Pending JPS54148481A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5657178A JPS54148481A (en) 1978-05-15 1978-05-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5657178A JPS54148481A (en) 1978-05-15 1978-05-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54148481A true JPS54148481A (en) 1979-11-20

Family

ID=13030819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5657178A Pending JPS54148481A (en) 1978-05-15 1978-05-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54148481A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009258721A (en) * 2008-04-11 2009-11-05 National Taiwan Univ Of Science & Technology Illusionary light source device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009258721A (en) * 2008-04-11 2009-11-05 National Taiwan Univ Of Science & Technology Illusionary light source device

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