JPS55123166A - Planar thyristor - Google Patents
Planar thyristorInfo
- Publication number
- JPS55123166A JPS55123166A JP3146079A JP3146079A JPS55123166A JP S55123166 A JPS55123166 A JP S55123166A JP 3146079 A JP3146079 A JP 3146079A JP 3146079 A JP3146079 A JP 3146079A JP S55123166 A JPS55123166 A JP S55123166A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- exposed
- diffusion
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 230000035945 sensitivity Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
- H01L29/102—Cathode base regions of thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
PURPOSE:To avoid the occurrence of erroneous operation by providing a shallow p<+>-type layer on the exposed parts of the junction of a p-type gate layer and an n<+>-type cathode layer in a planar thyristor in which the ends of all junctions are exposed to the surface. CONSTITUTION:In a p-type semiconductor substrate 1, which is to become an anode layer, an n-type base layer 2 is formed by diffusion. A p-type gate layer 3 is formed inside this, and further an n<+>-type cathode layer 4 is formed by diffusion in layer 3, and thereby a planar thyristor, with all junctions exposed to the surface, is constructed. In this structure, a shallow p<+>-type region 9 is formed by diffusion on the two exposed end surfaces of the pn-junction formed by layers 3 and 4. Then, the entire surface is covered with an SiO2 film 5, and by opening windows, a cathode 6 and a gate electrode 7 are fitted respectively on layers 4 and 3. On the back of substrate 1 is fitted anode 8. By this, it is possible to set the excessively sensitive gate current sensitivity at a proper value, so that no erroneous operation occures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3146079A JPS55123166A (en) | 1979-03-16 | 1979-03-16 | Planar thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3146079A JPS55123166A (en) | 1979-03-16 | 1979-03-16 | Planar thyristor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS55123166A true JPS55123166A (en) | 1980-09-22 |
Family
ID=12331864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3146079A Pending JPS55123166A (en) | 1979-03-16 | 1979-03-16 | Planar thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55123166A (en) |
-
1979
- 1979-03-16 JP JP3146079A patent/JPS55123166A/en active Pending
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