JPS5498580A - Field effect transistor - Google Patents

Field effect transistor

Info

Publication number
JPS5498580A
JPS5498580A JP552278A JP552278A JPS5498580A JP S5498580 A JPS5498580 A JP S5498580A JP 552278 A JP552278 A JP 552278A JP 552278 A JP552278 A JP 552278A JP S5498580 A JPS5498580 A JP S5498580A
Authority
JP
Japan
Prior art keywords
electrode
layer
chip
source
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP552278A
Other languages
Japanese (ja)
Other versions
JPS6128233B2 (en
Inventor
Masahide Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP552278A priority Critical patent/JPS5498580A/en
Publication of JPS5498580A publication Critical patent/JPS5498580A/en
Publication of JPS6128233B2 publication Critical patent/JPS6128233B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]

Abstract

PURPOSE:To avoid the deterioration in high frequency performance, by providing the second metal layer not reacted with the solder used for mounting chip on the source between electrodes, when the source electrode or drain electrode on chip is shortened wit the chip rear side by means of the first metallic layer. CONSTITUTION:After providing the source electrode 5, drain electrode 4 and gate electrode 5 on the surface of the N type semiconductor thin layer 2 formed on the semi-insulating substrate 1, the metal layer 7 of Pt not reacted with the solder such as AuGe, AuSi, and AuSn is coated on the electrode 3. The SiO2 layer 8 is formed on it and after pelletizing, the Au plating layer 6 is made on chip and the electrode 3 and the chip rear side are shortened by this. Thus, since no plating layer 6 is coated on the SiO2 layer 8, the reaction between the solder and Au stops here and no reaction advances on the electrode 3. Accordingly, the source current is excellently flowed via the layers 6 and 7 and no adverse effect on the performance can be made.
JP552278A 1978-01-20 1978-01-20 Field effect transistor Granted JPS5498580A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP552278A JPS5498580A (en) 1978-01-20 1978-01-20 Field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP552278A JPS5498580A (en) 1978-01-20 1978-01-20 Field effect transistor

Publications (2)

Publication Number Publication Date
JPS5498580A true JPS5498580A (en) 1979-08-03
JPS6128233B2 JPS6128233B2 (en) 1986-06-28

Family

ID=11613510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP552278A Granted JPS5498580A (en) 1978-01-20 1978-01-20 Field effect transistor

Country Status (1)

Country Link
JP (1) JPS5498580A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004079822A1 (en) * 2003-03-07 2004-09-16 Koninklijke Philips Electronics N.V. Semiconductor device, semiconductor body and method of manufacturing thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004079822A1 (en) * 2003-03-07 2004-09-16 Koninklijke Philips Electronics N.V. Semiconductor device, semiconductor body and method of manufacturing thereof

Also Published As

Publication number Publication date
JPS6128233B2 (en) 1986-06-28

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