JPS5496379A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS5496379A
JPS5496379A JP1014176A JP1014176A JPS5496379A JP S5496379 A JPS5496379 A JP S5496379A JP 1014176 A JP1014176 A JP 1014176A JP 1014176 A JP1014176 A JP 1014176A JP S5496379 A JPS5496379 A JP S5496379A
Authority
JP
Japan
Prior art keywords
trapping center
carrier
trapping
constitution
standard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1014176A
Other languages
Japanese (ja)
Inventor
Shiyunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP1014176A priority Critical patent/JPS5496379A/en
Publication of JPS5496379A publication Critical patent/JPS5496379A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To obtain a memory device of excellent performance by unifying the semiconductor memory possessing the nonvolatile trapping center and the standard MISFET in the series connection. CONSTITUTION:SiO2 thin film 2 is formed selectively at the gate region on the (100)-face of P-type Si1, and then insulator film 3 is coated through the reaction between SiH4 and NH4OH, with the Si semiconductor set as the trapping center of the positive hole and the electron. Then the gate electrode is attached. Thus, serial connected substance 22 of FET20 incorporating the trapping center in the gate insulator film is formed to standard MISFET21. The carrier is injected from the substrate of the gate electrode via the tunnel effect or the avalanche effect to perform trapping centering on the nonvolatile charge trapping center, and furthermore the trapped carrier turns on or off the channel right under the carrier. At the same time, the RAM function is secured. In this constitution, both the writing and reading is extremely easy with reduced number of wiring, thus ensuring production of a high-density memory being collected into the matrix array.
JP1014176A 1976-02-02 1976-02-02 Semiconductor memory device Pending JPS5496379A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1014176A JPS5496379A (en) 1976-02-02 1976-02-02 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1014176A JPS5496379A (en) 1976-02-02 1976-02-02 Semiconductor memory device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP4898771A Division JPS5760781B2 (en) 1971-07-03 1971-07-03

Publications (1)

Publication Number Publication Date
JPS5496379A true JPS5496379A (en) 1979-07-30

Family

ID=11741994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1014176A Pending JPS5496379A (en) 1976-02-02 1976-02-02 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5496379A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
US3577210A (en) * 1969-02-17 1971-05-04 Hughes Aircraft Co Solid-state storage device
JPS4829088A (en) * 1971-08-19 1973-04-17

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
US3577210A (en) * 1969-02-17 1971-05-04 Hughes Aircraft Co Solid-state storage device
JPS4829088A (en) * 1971-08-19 1973-04-17

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