JPS5490916A - Periodical pulse forming system in exchanging system - Google Patents

Periodical pulse forming system in exchanging system

Info

Publication number
JPS5490916A
JPS5490916A JP15917677A JP15917677A JPS5490916A JP S5490916 A JPS5490916 A JP S5490916A JP 15917677 A JP15917677 A JP 15917677A JP 15917677 A JP15917677 A JP 15917677A JP S5490916 A JPS5490916 A JP S5490916A
Authority
JP
Japan
Prior art keywords
pulse
bit
periodical
memory
pulse forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15917677A
Other languages
Japanese (ja)
Inventor
Kunio Yamamoto
Yasuo Miyazaki
Yasunori Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15917677A priority Critical patent/JPS5490916A/en
Publication of JPS5490916A publication Critical patent/JPS5490916A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q1/00—Details of selecting apparatus or arrangements
    • H04Q1/18—Electrical details
    • H04Q1/30—Signalling arrangements; Manipulation of signalling currents
    • H04Q1/39—Signalling arrangements; Manipulation of signalling currents using coded pulse groups

Abstract

PURPOSE:To obtain the periodical pulse in the exchanging system with comparatively simple configuratin, by reading out the content of memory. CONSTITUTION:''0'' and ''1'' are written in as shown in Fig. 3, in the memory (1). The 0 bit is the used to obtain the initialize condition, and the 1 bit to (n-1) bit are stored corresponding to the periodical pulse train of a given conditions. The basic pulse of a given period shorter than the pulse train repetitive period requested is inputted from 7, and the monotation address counter 2 performing address designation is advance. Every pulse is read out toward word and it is tentatively stored in the register 3, and the pulse trains of (n-2) types can be obtained from the terminal 5. For example, the output pulse of the second bit it ''L'' for first 2.5 sec. and ''HLH'' for every 0.5 second afterward and again returned to ''L''.
JP15917677A 1977-12-27 1977-12-27 Periodical pulse forming system in exchanging system Pending JPS5490916A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15917677A JPS5490916A (en) 1977-12-27 1977-12-27 Periodical pulse forming system in exchanging system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15917677A JPS5490916A (en) 1977-12-27 1977-12-27 Periodical pulse forming system in exchanging system

Publications (1)

Publication Number Publication Date
JPS5490916A true JPS5490916A (en) 1979-07-19

Family

ID=15687949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15917677A Pending JPS5490916A (en) 1977-12-27 1977-12-27 Periodical pulse forming system in exchanging system

Country Status (1)

Country Link
JP (1) JPS5490916A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4847259A (en) * 1971-10-08 1973-07-05
JPS5155661A (en) * 1974-11-12 1976-05-15 Fujitsu Ltd

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4847259A (en) * 1971-10-08 1973-07-05
JPS5155661A (en) * 1974-11-12 1976-05-15 Fujitsu Ltd

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